MMC2107 Datasheet, PDF (145/618 Pages) –

Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
Microarchitecture Summary
6.4 Microarchitecture Summary
Figure 6-1 is a block diagram of the M•CORE processor.
The processor utilizes a 4-stage pipeline for instruction execution. The
instruction fetch, instruction decode/register file read, execute, and
register file writeback stages operate in an overlapped fashion, allowing
single clock instruction execution for most instructions.
The execution unit consists of a 32-bit arithmetic/logic unit, a 32-bit
barrel shifter, a find-first-one unit, result feed-forward hardware, and
miscellaneous support hardware for multiplication, division, and
multiple-register loads and stores.
DATA CALCULATION
ADDRESS GENERATION
GENERAL-PURPOSE
REGISTER FILE
32 BITS X 16
X PORT
ALTERNATE
REGISTER FILE
32 BITS X 16
CONTROL
REGISTER FILE
32 BITS X 13
Y PORT
SCALE
IMMEDIATE
MUX
SIGN EXT.
BARREL SHIFTER
MULTIPLIER
DIVIDER
ADDRESS MUX
PC
INCREMENT
BRANCH
ADDER
ADDRESS
BUS
MUX
MUX
INSTRUCTION PIPELINE
ADDER/LOGICAL PRIORITY ENCODER/
ZERO DETECT RESULT MUX
WRITEBACK BUS
INSTRUCTION DECODE
H/W ACCELERATOR INTERFACE BUS DATA
BUS
Figure 6-1. M•CORE Processor Block Diagram
MMC2107 – Rev. 2.0
MOTOROLA
M•CORE M210 Central Processor Unit (CPU)
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Technical Data
145