MMC2107 Datasheet, PDF (570/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
21.14.5 OnCE Decoder (ODEC)
The ODEC receives as input the 8-bit command from the OCMR and
status signals from the processor. The ODEC generates all the strobes
required for reading and writing the selected OnCE registers.
21.14.6 Memory Breakpoint Logic
Memory breakpoints can be set for a particular memory location or on
accesses within an address range. The breakpoint logic contains an
input latch for addresses, registers that store the base address and
address mask, comparators, attribute qualifiers, and a breakpoint
counter. Figure 21-11 illustrates the basic functionality of the OnCE
memory breakpoint logic. This logic is duplicated to provide two
independent breakpoint resources.
DSCK
DSI
DSO
ADDR[31:0]
MEMORY ADDRESS LATCH
ADDRESS COMPARATOR
ATTR
BC[4:0], RCx
MATCH
MEMORY
BREAKPOINT
QUALIFICATION
ADDRESS BASE REGISTER X
ADDRESS MASK REGISTER X
BREAKPOINT
MATCH
OCCURRED
DEC
BREAKPOINT COUNTER
COUNT = 0
Technical Data
570
ISBKPTx
Figure 21-11. OnCE Memory Breakpoint Logic
JTAG Test Access Port and OnCE
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MMC2107 – Rev. 2.0
MOTOROLA