MMC2107 Datasheet, PDF (560/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
21.14.3.2 CPU Debug Request (DBGRQ)
The DBGRQ signal is asserted by the OnCE control logic to request the
CPU to enter the debug state. It may be asserted for a number of
different conditions. Assertion of this signal causes the CPU to finish the
current instruction being executed, save the instruction pipeline
information, enter debug mode, and wait for further commands.
Asserting DBGRQ causes the device to exit stop, doze, or wait mode.
21.14.3.3 CPU Debug Acknowledge (DBGACK)
The CPU asserts the DBGACK signal upon entering the debug state.
This signal is part of the handshake mechanism between the OnCE
control logic and the CPU.
21.14.3.4 CPU Breakpoint Request (BRKRQ)
The BRKRQ signal is asserted by the OnCE control logic to signal that
a breakpoint condition has occurred for the current CPU bus access.
21.14.3.5 CPU Address, Attributes (ADDR, ATTR)
The CPU address and attribute information may be used in the memory
breakpoint logic to qualify memory breakpoints with access address and
cycle type information.
21.14.3.6 CPU Status (PSTAT)
The trace logic uses the PSTAT signals to qualify trace count
decrements with specific CPU activity.
21.14.3.7 OnCE Debug Output (DEBUG)
The DEBUG signal is used to indicate to on-chip resources that a debug
session is in progress. Peripherals and other units may use this signal to
modify normal operation for the duration of a debug session. This may
involve the CPU executing a sequence of instructions solely for the
purpose of visibility/system control. These instructions are not part of the
normal instruction stream that the CPU would have executed had it not
been placed in debug mode.
Technical Data
560
JTAG Test Access Port and OnCE
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MMC2107 – Rev. 2.0
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