MMC2107 Datasheet, PDF (508/618 Pages) –

Freescale Semiconductor, Inc.
External Bus Interface Module (EBI)
19.4 Memory Map and Registers
The EBI is not memory-mapped and has no software-accessible
registers.
19.5 Operand Transfer
The possible operand accesses for the internal M•CORE bus are:
• Byte
• Aligned upper half-word
• Aligned lower half-word
• Aligned word
No misaligned transfers are supported. The EBI controls the byte,
half-word, or word operand transfers between the M•CORE bus and a
16-bit or 32-bit port. “Port” refers to the width of the data path that an
external device uses during a data transfer. Each port is assigned to
particular bits of the data bus. A 16-bit port is assigned to pins D[31:16]
and a 32-bit port is assigned to pins D[31:0].
In the case of a word (32-bit) access to a 16-bit port, the EBI runs two
external bus cycles to complete the transfer. During the first external bus
cycle, the A[1:0] pins are driven low, and the TSIZ[1:0] pins are driven to
indicate word size. During the second cycle, A1 is driven high to
increment the external address by two bytes, A0 is still driven low, and
the TSIZ[1:0] pins are driven to indicate half-word size.
During any word-size transfer, the EBI always drives the A[1:0] pins low
during a word transfer (except on the second cycle of a word to half-word
port transfer in which A1 is incremented).
Table 19-2 shows each possible transfer size, alignment, and port width.
The data bytes shown in the table represent external data pins. This data
is multiplexed and driven to the external data bus as shown. The bytes
labeled with a dash are not required; the M•CORE will ignore them on
read transfers, and drive them with undefined data on write transfers.
Technical Data
508
External Bus Interface Module (EBI)
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Go to: www.freescale.com
MMC2107 – Rev. 2.0
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