MMC2107 Datasheet, PDF (433/618 Pages) –

MMC2107 – Rev. 2.0
MOTOROLA
Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
The two most significant bits are associated primarily with queue 1,
and the remaining two bits are associated with queue 2. Since the
priority scheme between the two queues causes the status to be
interlinked, the status bits are considered as one 4-bit field.
Table 18-8 shows the bits in the QS field and how they affect the
status of queue 1 and queue 2.
One or both queues may be in the idle state. When a queue is idle,
CCWs are not being executed for that queue, the queue is not in the
pause state, and there is not a trigger pending.
The idle state occurs when a queue is disabled, when a queue is in a
reserved mode, or when a queue is in a valid queue operating mode
awaiting a trigger event to initiate queue execution.
Table 18-8. Queue Status
QS[9:6]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Queue 1/Queue 2 States
Queue 1 idle, queue 2 idle
Queue 1 idle, queue 2 paused
Queue 1 idle, queue 2 active
Queue 1 idle, queue 2 trigger pending
Queue 1 paused, queue 2 idle
Queue 1 paused, queue 2 paused
Queue 1 paused, queue 2 active
Queue 1 paused, queue 2 trigger pending
Queue 1 active, queue 2 idle
Queue 1 active, queue 2 paused
Queue 1 active, queue 2 suspended
Queue 1 active, queue 2 trigger pending
Reserved
Reserved
Reserved
Reserved
A queue is in the active state when a valid queue operating mode is
selected, when the selected trigger event has occurred, or when the
QADC is performing a conversion specified by a CCW from that
queue.
Queued Analog-to-Digital Converter (QADC)
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Technical Data
433