MMC2107 Datasheet, PDF (437/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
During the stop mode, the CWPQ1 is reset to 63 (0x3f), since the
control registers and the analog logic are reset. When the debug
mode is entered, the CWPQ1 is unchanged; it points to the last
executed CCW in queue 1.
CWPQ2[5:0] — Queue 2 Command Word Pointer Field
CWPQ2[5:0] allows the software to know what CCW was last
completed for queue 2. This field is a software read-only field, and
write operations have no effect. CWPQ2[5:0] allows software to read
the last executed CCW in queue 2, regardless which queue is active.
The CWPQ2[5:0] field is a CCW word pointer with a valid range of 0
to 63.
In contrast to CWP, CPWQ2 is updated when the conversion result is
written. When the QADC finishes a conversion in queue 2, both the
result register is written and the CWPQ2 are updated.
During the stop mode, the CWPQ2 is reset to 63, since the control
registers and the analog logic are reset. When the debug mode is
entered, the CWP is unchanged; it points to the last executed CCW
in queue 2.
18.8.7 Conversion Command Word Table
Address: 0x00ca_0200 through 0x00ca_027e
Bit 15
14
13
12
11
10
9
Bit 8
Read: 0
0
0
0
0
0
P
BYP
Write:
Reset: 0
0
0
0
0
0
U
U
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IST1
Write:
IST0 CHAN5 CHAN4 CHAN3 CHAN2 CHAN1 CHAN0
Reset: U
U
U
U
U
U
U
U
= Writes have no effect and the access terminates without a transfer error exception.
U = Unaffected
Figure 18-14. Conversion Command Word Table (CCW)
MMC2107 – Rev. 2.0
MOTOROLA
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
437