MMC2107 Datasheet, PDF (245/618 Pages) –

Freescale Semiconductor, Inc.
Clock Module
Functional Description
10.8.6.1 Phase and Frequency Detector (PFD)
The PFD is a dual-latch phase-frequency detector. It compares both the
phase and frequency of the reference and feedback clocks. The
reference clock comes from either the crystal oscillator or an external
clock source. The feedback clock comes from:
• CLKOUT in 1:1 PLL mode, or
• VCO output divided by two if CLKOUT is disabled in 1:1 PLL
mode, or
• VCO output divided by the MFD in normal PLL mode
When the frequency of the feedback clock equals the frequency of the
reference clock, the PLL is frequency-locked. If the falling edge of the
feedback clock lags the falling edge of the reference clock, the PFD
pulses the UP signal. If the falling edge of the feedback clock leads the
falling edge of the reference clock, the PFD pulses the DOWN signal.
The width of these pulses relative to the reference clock depends on how
much the two clocks lead or lag each other. Once phase lock is
achieved, the PFD continues to pulse the UP and DOWN signals for very
short durations during each reference clock cycle. These short pulses
continually update the PLL and prevent the frequency drift phenomenon
known as dead-banding.
10.8.6.2 Charge Pump/Loop Filter
In 1:1 PLL mode, the charge pump uses a fixed current. In normal mode
the current magnitude of the charge pump varies with the MFD as shown
in Table 10-9.
Table 10-9. Charge Pump Current and MFD
in Normal Mode Operation
Charge Pump Current
1X
2X
4X
MFD
0 ≤ MFD < 2
2 ≤ MFD < 6
6 ≤ MFD
The UP and DOWN signals from the PFD control whether the charge
pump applies or removes charge, respectively, from the loop filter. The
filter is integrated on the chip.
MMC2107 – Rev. 2.0
MOTOROLA
Clock Module
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Technical Data
245