MMC2107 Datasheet, PDF (417/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
TRG — Trigger Assignment Bit
The TRG bit allows the software to assign the ETRIG[2:1] pins to
queue 1 and queue 2.
1 = ETRIG1 triggers queue 2, ETRIG2 triggers queue 1
0 = ETRIG1 triggers queue 1, ETRIG2 triggers queue 2
PSH[8:4] — Prescaler Clock High Time Field
The PSH field selects the QCLK high time in the prescaler.
See Section 22. Electrical Specifications for operating
clock frequency (f_QCLK) values. To keep the QCLK within the specified
range, the PSH field selects the high time of the QCLK, which can
range from 1 to 32 system clock cycles. The minimum high time for
the QCLK is specified as t_PSH. Table 18-3 displays the bits in PSH field
which enable a range of QCLK high times.
Table 18-3. Prescaler Clock High Times
PSH[8:4] QCLK High Time
00000 1 system clock cycle
00001 2 system clock cycles
00010 3 system clock cycles
00011 4 system clock cycles
00100 5 system clock cycles
00101 6 system clock cycles
00110 7 system clock cycles
00111 8 system clock cycles
01000 9 system clock cycles
01001 10 system clock cycles
01010 11 system clock cycles
01011 12 system clock cycles
01100 13 system clock cycles
01101 14 system clock cycles
01110 15 system clock cycles
01111 16 system clock cycles
PSH[8:4] QCLK High Time
10000 17 system clock cycles
10001 18 system clock cycles
10010 19 system clock cycles
10011 20 system clock cycles
10100 21 system clock cycles
10101 22 system clock cycles
10110 23 system clock cycles
10111 24 system clock cycles
11000 25 system clock cycles
11001 26 system clock cycles
11010 27 system clock cycles
11011 28 system clock cycles
11100 29 system clock cycles
11101 30 system clock cycles
11110 31 system clock cycles
11111 32 system clock cycles
MMC2107 – Rev. 2.0
MOTOROLA
Queued Analog-to-Digital Converter (QADC)
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Technical Data
417