MMC2107 Datasheet, PDF (307/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
Memory Map and Registers
15.7.8 Timer Control Register 1
Address: TIM1 — 0x00ce_0009
TIM2 — 0x00cf_0009
Bit 7
6
5
4
3
2
1
Bit 0
Read:
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
Write:
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 15-11. Timer Control Register 1 (TIMCTL1)
Read: Anytime
Write: Anytime
OMx/OLx — Output Mode/Output Level Bits
These bit pairs select the output action to be taken as a result of a
successful output compare. When either OMx or OLx is set and the
IOSx bit is set, the pin is an output regardless of the state of the
corresponding DDR bit.
Table 15-3. Output Compare Action Selection
OMx:OLx
00
01
10
11
Action on Output Compare
Timer disconnected from output pin logic
Toggle OCx output line
Clear OCx output line
Set OCx line
Channel 3 shares a pin with the pulse accumulator input pin. To use
the PAI input, clear both the OM3 and OL3 bits and clear the OC3M3
bit in the output compare 3 mask register.
MMC2107 – Rev. 2.0
MOTOROLA
Timer Modules (TIM1 and TIM2)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
307