MMC2107 Datasheet, PDF (548/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
signals.To maintain JTAG compliance, TEST should be held to logic 0
and DE should be held to logic 1. These non-scanned pins are shown in
Table 21-2.
Table 21-2. List of Pins Not Scanned in JTAG Mode
Pin Name
EXTAL
XTAL
V_DDSYN
V_SSSYN
PQA4–PQA3 and PQA1–PQA0
PQB3–PQB0
V_RH
V_RL
V_DDA
V_SSA
V_DDH
TRST
TCLK
TMS
TDI
TDO
DE
TEST
V_pp
V_DDF
V_SSF
V_STBY
V_DD
V_SS
Pin Type
Clock/analog
Clock/analog
Supply
Supply
Analog
Analog
Supply
Supply
Supply
Supply
Supply
JTAG
JTAG
JTAG
JTAG
JTAG
JTAG compliance enable
JTAG compliance enable
Supply
Supply
Supply
Supply
Supply
Supply
Technical Data
548
JTAG Test Access Port and OnCE
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA