MMC2107 Datasheet, PDF (416/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
18.8.5 Control Registers
This subsection describes the QADC control registers.
18.8.5.1 Control Register 0
Control register 0 (QACR0) establishes the QCLK with prescaler
parameter fields and defines whether external multiplexing is enabled.
They are typically written once when the software initializes the QADC
and not changed afterward.
Address: 0x00ca_000a and 0x00ca_000b
Bit 15
14
13
12
11
10
9
Bit 8
Read:
0
0
0
0
0
MUX
TRG
PSH8
Write:
Reset: 0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PSH7 PSH6 PSH5 PSH4
PSA
PSL2 PSL1 PSL0
Write:
Reset: 0
0
1
1
0
1
1
1
= Writes have no effect and the access terminates without a transfer error exception.
Figure 18-8. QADC Control Register 0 (QACR0)
Read: Anytime
Write: Anytime except stop mode
MUX — Externally Multiplexed Mode Bit
The MUX bit allows the software to select the externally multiplexed
mode, which affects the interpretation of the channel numbers and
forces the MA[1:0] pins to be outputs.
1 = Externally multiplexed, 18 possible channels
0 = Internally multiplexed, eight possible channels
Technical Data
416
Queued Analog-to-Digital Converter (QADC)
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Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA