MMC2107 Datasheet, PDF (411/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
18.8 Register Descriptions
This subsection describes the QADC registers.
18.8.1 QADC Module Configuration Register
The QADCMCR contains fields and bits that control freeze and stop
modes and determines the privilege level required to access most
registers.
Address: 0x00ca_0000 and 0x00ca_0001
Bit 15
14
13
12
11
10
9
Bit 8
Read:
0
0
0
0
0
0
QSTOP QDBG
Write:
Reset: 0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
SUPV
Write:
Reset: 1
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 18-3. QADC Module Configuration Register (QADCMCR)
QSTOP — Stop Enable Bit
1 = Forces QADC to idle state
0 = QADC is not forced to idle state
QDBG — Debug Enable Bit
1 = Finish any conversion in progress, then freezes in debug mode
0 = Ignore request to enter debug mode and continue conversions
SUPV — Supervisor/Unrestricted Data Space Bit
1 = Only supervisor mode access allowed; user mode accesses
have no effect and result in a cycle termination transfer error
0 = Supervisor and user mode accesses allowed
MMC2107 – Rev. 2.0
MOTOROLA
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
411