MMC2107 Datasheet, PDF (466/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Another pause and end-of-queue boundary condition occurs when the
pause and an end-of-queue condition occur in the same CCW. Both the
pause and end-of-queue conditions are recognized simultaneously. The
end-of-queue condition has precedence so a conversion is not
performed for the CCW and the pause flag is not set. The QADC sets the
completion flag and the queue status becomes idle. Examples of this
situation are:
• The pause bit is set in CCW10 and EOQ is programmed into
CCW10.
• During queue 1 operation, the pause bit set in CCW32, which is
also BQ2.
18.10.3 Scan Modes
The QADC queuing mechanism allows the application to utilize different
requirements for automatically scanning input channels.
In single-scan mode, a single pass through a sequence of conversions
defined by a queue is performed. In continuous-scan mode, multiple
passes through a sequence of conversions defined by a queue are
executed. The possible modes are:
• Disabled mode and reserved mode
• Software-initiated single-scan mode
• External trigger single-scan mode
• External gated single-scan mode
• Interval timer single-scan mode
• Software-initiated continuous-scan mode
• External trigger continuous-scan mode
• External gated continuous-scan mode
• Periodic timer continuous-scan mode
These paragraphs describe single-scan and continuous-scan
operations.
Technical Data
466
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA