MMC2107 Datasheet, PDF (553/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Low-Level TAP (OnCE) Module
21.12 Low-Level TAP (OnCE) Module
The low-level TAP (OnCE, on-chip emulation) circuitry provides a
simple, inexpensive debugging interface that allows external access to
the processor’s internal registers and to memory/peripherals. OnCE
capabilities are controlled through a serial interface, mapped onto a
JTAG test access port (TAP) protocol.
Refer to Figure 21-4 for a block diagram of the OnCE.
NOTE: The interface to the OnCE controller and its resources is based on the
TAP defined for JTAG in the IEEE 1149.1 standard.
PIPELINE
INFORMATION
PC
FIFO
BREAKPOINT
AND TRACE
LOGIC
BREAKPOINT
REGISTERS
AND
COMPARATORS
OnCE
CONTROLLER
AND SERIAL
INTERFACE
TCLK
TDI
TMS
TDO
TRST
DE
Figure 21-4. OnCE Block Diagram
Figure 21-5 shows the OnCE (low-level TAP module) data registers in
the MMC2107.
MMC2107 – Rev. 2.0
MOTOROLA
JTAG Test Access Port and OnCE
For More Information On This Product,
Go to: www.freescale.com
Technical Data
553