MMC2107 Datasheet, PDF (514/618 Pages) –

Freescale Semiconductor, Inc.
External Bus Interface Module (EBI)
19.7.2.1 State 1 (X1)
The EBI drives the address bus. The TSIZ[1:0] pins are driven to indicate
the number of bytes in the transfer. TC[2:0] pins are driven to indicate
the type of access. CS may be asserted to drive a device. OE is negated.
Later in state 1, R/W is driven low indicating a write cycle. One or more
EB pins are asserted, depending on the size and position of the data to
be transferred.
If either the external TA pin or internal chip-select transfer acknowledge
signal is asserted before the end of state 1, the EBI proceeds to state 2.
19.7.2.2 Optional Wait States (X2W)
Wait states are inserted until the slave asserts the TA pin or the internal
chip-select transfer acknowledge signal is asserted. The EBI drives its
data onto data bus lines D[31:16] and/or D[15:0] on the first optional wait
state. Wait states are counted in full clocks.
19.7.2.3 State 2 (X2)
If the data was not already driven during optional wait states, the EBI
drives its data onto D[31:16] and/or D[15:0] in state 2.
EB is negated by the end of state 2. The address bus, data bus, R/W,
CS, TC[2:0], and TSIZ[1:0] pins remain valid through state 2 to allow for
static memory operation and signal skew.
Figure 19-3 and Figure 19-4 illustrate external bus master cycles with
and without wait states and show M•CORE bus activity.
Technical Data
514
External Bus Interface Module (EBI)
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MMC2107 – Rev. 2.0
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