MMC2107 Datasheet, PDF (528/618 Pages) –

Freescale Semiconductor, Inc.
Chip Select Module
read/write signal, which indicates whether the access is a read
(read/write = 1) or a write (read/write = 0). If the chip select logic
detects a violation (RO = 1 with read/write = 0), the access is ignored.
1 = Only read accesses allowed; write accesses ignored by the
chip select logic
0 = Read and write accesses allowed
PS — Port Size Bit
The PS bit defines the width of the external data port supported by the
chip select as either 16-bit or 32-bit. When a chip select is
programmed as a 16-bit port, the external device must be connected
to D[31:16]. For 32-bit accesses to 16-bit ports, the external memory
interface initiates two bus cycles and multiplexes data as needed to
complete the data transfer.
1 = 32 bit port
0 = 16 bit port
WWS — Write Wait State Bit
The WWS bit determines if an additional wait state is required for write
cycles. WWS does not affect read cycles.
1 = One additional wait state added for write cycles
0 = No additional wait state added for write cycles
WE — Write Enable Bit
The WE bit defines when the enable byte output pins (EB[3:0]) are
asserted. When WE is 0, EB[3:0] are configured as byte enables and
assert for both external read and external write accesses. When WE
is 1, EB[3:0] are configured as write enables and assert only for
external write accesses.
1 = EB[3:0] configured as write enables
0 = EB[3:0] configured as byte enables
NOTE:
The WE bit has no effect on the EB[3:0] pin function if the chip select is
not active. If the chip select is not active, the EB[3:0] pin function is byte
enable by default.
WS[2:0] — Wait States Field
The WS field determines the number of wait states for the chip select
logic to insert before asserting the internal cycle termination signal.
One wait state is equal to one system clock cycle. If WS is configured
for zero wait states, then the internal cycle termination signal is
Technical Data
528
Chip Select Module
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MMC2107 – Rev. 2.0
MOTOROLA