CP3BT23_14 Datasheet, PDF (99/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
SLE is the alternate function of the general-purpose I/O pin PG5. At reset, this pin is in TRI-STATE mode.
Software must enable the alternate function of the PG5 pin to give control over this signal to the RF
interface.
BTSEQ[3:1]
The BTSEQ[3:1] signals indicate internal states of the Bluetooth sequencer, which are used for interfacing
to some external devices.
15.2 SERIAL INTERFACE
The radio chip register set can be accessed by the CP3BT23 through the serial interface. The serial
interface uses three pins of the RF interface: SDAT, SCLK, and SLE.
The serial interface of the CP3BT23 always operates as the master, providing the shift clock (SCLK) and
load enable (SLE) signal to the radio chip. The radio chip always acts as the slave.
A 25-bit shift protocol is used to perform read/write accesses to the radio chip internal registers. The
complete protocol is comprised of the following sections:
• 3-bit Header Field
• Read/Write Bit
• 5-bit Address Field
• 16-bit Data Field
Header
The 3-bit header contains the fixed data 101b (except for Fast Write Operations).
Read/Write Bit
The header is followed by the read/write control bit (R/W). If the Read/Write bit is clear, a write operation
is performed and the 16-bit data portion is copied into the addressed radio chip register.
Address
The address field is used to select one of the radio chip internal registers.
Data
The data field is used to transfer data to or from a radio chip register. The timing is modified for reads, to
transfer control over the data signal from the CP3BT23 to the radio chip.
shows the serial interface protocol format.
Data is transferred on the serial interface with the most significant bit (MSB) first.
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