CP3BT23_14 Datasheet, PDF (207/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
21.2.8 DMA Support
The UART module can operate with one or two DMA channels. Two DMA channels must be used for
processor-independent full-duplex operation. Both receive and transmit DMA can be enabled
simultaneously.
If transmit DMA is enabled (the UETD bit is set), the UART generates a DMA request when the UTBE bit
changes state from clear to set. Enabling transmit DMA automatically disables transmit interrupts, without
regard to the state of the UETI bit.
If receive DMA is enabled (the UERD bit is set), the UART generates a DMA request when the URBF bit
changes state from clear to set. Enabling receive DMA automatically disables receive interrupts, without
regard to the state of the UERI bit. However, receive error interrupts should be enabled (the UEEI bit is
set) to allow detection of receive errors when DMA is used.
21.2.9 Break Generation and Detection
A line break is generated when the UBRK bit is set in the UnMDSL1 register. The TXD line remains low
until the program resets the UBRK bit.
A line break is detected if RXD remains low for 10 bit times or longer after a missing stop bit is detected.
21.2.10 Parity Generation and Detection
Parity is only generated or checked with the 7-bit and 8-bit data formats. It is not generated or checked in
the diagnostic loopback mode, the attention mode, or in normal mode with the 9-bit data format. Parity
generation and checking are enabled and disabled using the PEN bit in the UnFRS register. The UPSEL
bits in the UnFRS register are used to select odd, even, or no parity.
21.3 UART Registers
Software interacts with the UART modules by accessing the UART registers, as listed in Table 21-2.
Name
U0RBUF
U0TBUF
U0PSR
U0BAUD
U0FRS
U0MDSL
U0STAT
U0ICTRL
U0OVR
U0MDSL2
U0SPOS
U1RBUF
U1TBUF
U1PSR
U1BAUD
U1FRS
U1MDSL1
U1STAT
U1ICTRL
U1OVR
U1MDSL2
Table 21-2. UART Registers
Address
FF F202h
FF F200h
FF F20Eh
FF F20Ch
FF F208h
FF F20Ah
FF F206h
FF F204h
FF F210h
FF F212h
FF F214h
FF F222h
FF F220h
FF F22Eh
FF F22Ch
FF F228h
FF F22Ah
FF F226h
FF F224h
FF F230h
FF F232h
Description
UART0 Receive Data Buffer
UART0 Transmit Data Buffer
UART0 Baud Rate Prescaler
UART0 Baud Rate Divisor
UART0 Frame Select Register
UART0 Mode Select Register 1
UART0 Status Register
UART0 Interrupt Control Register
UART0 Oversample Rate Register
UART0 Mode Select Register 2
UART0 Sample Position Register
UART1 Receive Data Buffer
UART1 Transmit Data Buffer
UART1 Baud Rate Prescaler
UART1 Baud Rate Divisor
UART1 Frame Select Register
UART1 Mode Select Register 1
UART1 Status Register
UART1 Interrupt Control Register
UART1 Oversample Rate Register
UART1 Mode Select Register 2
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