CP3BT23_14 Datasheet, PDF (211/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
21.3.7 UART Status Register (UnSTAT)
The UnSTAT register is a byte-wide, read-only register that contains the receive and transmit status bits.
This register is cleared upon reset. Any attempt by software to write to this register is ignored. The register
format is shown below.
7
Res.
6
UXMIP
5
URB9
4
UBKD
3
UERR
2
UDOE
1
UFE
0
UPE
UPE
UFE
UDOE
UERR
UBKD
URB9
UXMIP
The Parity Error bit indicates whether a parity error is detected within a received character.
This bit is automatically cleared by the hardware when the UnSTAT register is read.
0 – No parity error occurred.
1 – Parity error occurred.
The Framing Error bit indicates whether the UART fails to receive a valid stop bit at the end
of a frame. This bit is automatically cleared by the hardware when the UnSTAT register is
read.
0 – No framing error occurred.
1 – Framing error occurred.
The Data Overrun Error bit is set when a new character is received and transferred to the
UnRBUF register before software has read the previous character from the UnRBUF
register. This bit is automatically cleared by the hardware when the UnSTAT register is
read.
0 – No receive overrun error occurred.
1 – Receive overrun error occurred.
The Error Status bit indicates when a parity, framing, or overrun error occurs (any time that
the UPE, UFE, or UDOE bit is set). It is automatically cleared by the hardware when the
UPE, UFE, and UDOE bits are all 0.
0 – No receive error occurred.
1 – Receive error occurred.
The Break Detect bit indicates when a line break condition occurs. This condition is detected
if RXD remains low for at least ten bit times after a missing stop bit has been detected at the
end of a frame. The hardware automatically clears the UBKD bit on reading the UnSTAT
register, but only if the break condition on RXD no longer exists. If reading the UnSTAT
register does not clear the UBKD bit because the break is still actively driven on the line, the
hardware clears the bit as soon as the break condition no longer exists (when the RXD input
returns to a high level).
0 – No break condition occurred.
1 – Break condition occurred.
The Received 9th Data Bit holds the ninth data bit, when the UART is configured to operate
in the 9-bit data format.
The Transmit In Progress bit indicates when the UART is transmitting. The hardware sets
this bit when the UART is transmitting data and clears the bit at the end of the last frame bit.
0 – UART is not transmitting.
1 – UART is transmitting.
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