CP3BT23_14 Datasheet, PDF (139/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
18.5.1 Receive Timing
As soon as the CAN module receives a “dominant” bit on the CAN bus, the receive process is started. The
received ID and data will be stored in the hidden receive buffer if the global or basic acceptance filtering
matches. After the reception of the data, CAN module tries to match the buffer ID of buffer 0...14. The
data will be copied into the buffer after the reception of the 6th EOF bit as a message is valid at this time.
The copy process of every frame, regardless of the length, takes at least 17 CKI cycles (see also
Section 18.9.1). Figure 18-20 shows the receive timing.
BUS
BUS
IDLE
SOF
1 BIT
ARBITRATION FIELD
+ CONTROL
12/29 BIT + 6 BIT
DATA FIELD
(IF PRESENT)
n × 8 BIT
CRC
FIELD
16 BIT
ACK
FIELD
2 BIT
EOF
7 BIT
IFS
3 BIT
rx_start
BUSY
Copy to Buffer
DS037
Figure 18-20. Receive Timing
o indicate that a frame is waiting in the hidden buffer, the BUSY bit (ST[0]) of the selected buffer is set
during the copy procedure. The BUSY bit will be cleared by the CAN module immediately after the data
bytes are copied into the buffer. After the copy process is finished, the CAN module changes the status
field to RX_FULL. In turn, the CPU should change the status field to RX_READY when the data is
processed. When a new object has been received by the same buffer, before the CPU changed the status
to RX_READY, the CAN module will change the status to RX_OVERRUN to indicate that at least one
frame has been overwritten by a new one. Table 18-3 summarizes the current status and the resulting
update from the CAN module.
RX_READY
RX_NOT_ACTIVE
RX_FULL
Table 18-3. Writing to Buffer Status Code During RX_BUSY
Current Status
RX_FULL
RX_NOT_ACTIVE
RX_OVERRUN
Resulting Status
During the assertion of the BUSY bit, all writes to the receiving buffer are disabled with the exception of
the status field. If the status is changed while the BUSY bit is asserted, the status is updated by the CAN
module as shown in Table 18-3.
The buffer states are indicated and controlled by the ST[3:0] bits in the CNSTAT register (see
Section 18.10.1. The various receive buffer states are explained in Section 18.5.3.
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