CP3BT23_14 Datasheet, PDF (295/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
29.11 UART TIMING
Table 29-3. UART Signals
Symbol
t_CKX
t_RXS
t_RXH
t_TXD
Figure
Description
Reference
UART Input Signals
Figure 29-5 CKX period (synchronous mode)
Figure 29-5 RXD setup time (synchronous mode) Before Falling Edge (FE) on CKX
Figure 29-5 RXD hold time (synchronous mode) Before FE on CKX
UART Output Signals
Figure 29-5 TXD output valid (synchronous mode) After Rising Edge (RE) on CKX
Min (ns)
250
40
40
–
Max (ns)
–
–
–
40
t_CKX
CKX
TXD
t_TXD
t_RXS
RXD
t_RXH
DS099
Figure 29-5. UART Synchronous Mode Timing
29.12 I/O Port Timing
Table 29-4. I/O Port Signals
Symbol
Figure
Description
t_IS
Figure 29-6 Input Setup Time
t_IH
Figure 29-6 Input Hold Time
t_COv1 Figure 29-6 Output Valid Time
Reference
I/O Port Input Signals
Before Falling Edge (FE) on System
Clock
After FE on System Clock
I/O Port Output Signals
After FE on System Clock
Min (ns)
22.5
0
–
Max (ns)
–
–
3
Figure 29-6. I/O Port Timing
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Electrical Characteristics 295