CP3BT23_14 Datasheet, PDF (175/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
19.5.3 Normal Mode
In normal mode, each frame sync signal marks the beginning of a new frame and also the beginning of a
new slot, since each frame only consists of one slot. All 16 receive and transmit FIFO locations hold data
for the same (and only) slot of a frame. If 8-bit data are transferred, only the low byte of each 16-bit FIFO
location holds valid data.
19.5.4 Transmit
Once the interface has been enabled, transmit transfers are initiated automatically at the beginning of
every frame. The beginning of a new frame is identified by a frame sync pulse. Following the frame sync
pulse, the data is shifted out from the ATSR to the STD pin on the positive edge of the transmit data shift
clock (SCK).
DMA Operation
When a complete data word has been transmitted through the STD pin, a new data word is reloaded from
the transmit DMA register 0 (ATDR0). A DMA request is asserted when the ATDR0 register is empty. If a
new data word must be transmitted while the ATDR0 register is still empty, the previous data will be re-
transmitted.
FIFO Operation
When a complete data word has been transmitted through the STD pin, a new data word is loaded from
the transmit FIFO from the current location of the Transmit FIFO Read Pointer (TRP). After that, the TRP
is automatically incremented by 1.
A write to the Audio Transmit FIFO Register (ATFR) results in a write to the transmit FIFO at the current
location of the Transmit FIFO Write Pointer (TWP). After every write operation to the transmit FIFO, TWP
is automatically incremented by 1.
When the TRP is equal to the TWP and the last access to the FIFO was a read operation (a transfer to
the ATSR), the transmit FIFO is empty. When an additional read operation from the FIFO to ATSR is
performed (while the FIFO is already empty), a transmit FIFO underrun occurs. In this event, the read
pointer (TRP) will be decremented by 1 (incremented by 15) and the previous data word will be
transmitted again. A transmit FIFO underrun is indicated by the TXU bit in the Audio Interface Transmit
Status and Control Register (ATSCR). Also, no transmit interrupt will be generated (even if enabled).
When the TRP is equal to the TWP and the last access to the FIFO was a write operation (to the ATFR),
the FIFO is full. If an additional write to ATFR is performed, a transmit FIFO overrun occurs. This error
condition is not prevented by hardware. Software must ensure that no transmit overrun occurs.
The transmit frame synchronization pulse on the SFS pin and the transmit shift clock on the SCK pin may
be generated internally, or they can be supplied by an external source.
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