CP3BT23_14 Datasheet, PDF (134/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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The phase error is given by the deviation of the edge to the SYNC segment, measured in CAN clocks.
The value of the phase error is defined as:
e = 0, if the edge occurs within the SYNC segment
e > 0, if the edge occurs within TSEG1
e < 0, if the edge occurs within TSEG2 of the previous bit
Resynchronization is performed according to the following rules:
• If the magnitude of e is less then or equal to the programmed value of SJW, resynchronization will
have the same effect as hard synchronization.
• If e > SJW, TSEG1 will be lengthened by the value of the SJW (see Figure 18-12).
• If e < -SJW, TSEG2 will be shortened by the value SJW (see Figure 18-13).
e
Bus
Signal
CAN
Clock
PREVIOUS
BIT
A
TSEG1
"NORMAL" BIT TIME
TSEG2
NEXT BIT
PREVIOUS
BIT
A
TSEG1
SJW
BIT TIME LENGTHENED BY SJW
TSEG2
Figure 18-12. Resynchronization (e > SJW)
NEXT BIT
DS029
e
Bus
Signal
CAN
Clock
PREVIOUS
BIT
A
TSEG1
"NORMAL" BIT TIME
TSEG2
PREVIOUS
BIT
A
TSEG1
BIT TIME SHORTENED BY SJW
TSEG2
Figure 18-13. Resynchronization (e < -SJW)
NEXT BIT
DS030
134 CAN Module
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