CP3BT23_14 Datasheet, PDF (254/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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25.5.3 Timer/Counter 1 Register (TCNT1)
The TCNT1 register is a word-wide, read/write register that holds the current count value for
Timer/Counter 1. The register contents are not affected by a reset and are unknown after power-up.
15
0
TCNT1
25.5.4 Timer/Counter 2 Register (TCNT2)
The TCNT2 register is a word-wide, read/write register that holds the current count value for
Timer/Counter 2. The register contents are not affected by a reset and are unknown after power-up.
15
0
TCNT2
25.5.5 Reload/Capture A Register (TCRA)
The TCRA register is a word-wide, read/write register that holds the reload or capture value for
Timer/Counter 1. The register contents are not affected by a reset and are unknown after power-up.
15
0
TCRA
25.5.6 Reload/Capture B Register (TCRB)
The TCRB register is a word-wide, read/write register that holds the reload or capture value for
Timer/Counter 2. The register contents are not affected by a reset and are unknown after power-up.
15
0
TCRB
25.5.7 Timer Mode Control Register (TCTRL)
The TCTRL register is a byte-wide, read/write register that sets the operating mode of the timer/counter
and the TA and TB pins. This register is cleared at reset. The register format is shown below.
7
TEN
6
TAOUT
5
TBEN
4
TAEN
3
TBEDG
2
TAEDG
1
0
MDSEL
MDSEL
TAEDG
TBEDG
The Mode Select field sets the operating mode of the timer/counter as follows:
00 – Mode 1: PWM plus system timer.
01 – Mode 2: Dual-Input Capture plus system timer.
10 – Mode 3: Dual Timer/Counter.
11 – Mode 4: Single-Input Capture and Single Timer.
The TA Edge Polarity bit selects the polarity of the edges that trigger the TA input.
0 – TA input is sensitive to falling edges (high to low transitions).
1 – TA input is sensitive to rising edges (low to high transitions).
The TB Edge Polarity bit selects the polarity of the edges that trigger the TB input. In
pulseaccumulate mode, when this bit is set, the counter is enabled only when TB is high;
when this bit is clear, the counter is enabled only when TB is low.
0 – TB input is sensitive to falling edges (high to low transitions).
1 – TB input is sensitive to rising edges (low to high transitions).
254 Multi-Function Timer
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