CP3BT23_14 Datasheet, PDF (49/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
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SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
8.5.18 Flash Memory Auto-Read Register 1 (FMAR1/ FSMAR1)
The FMAR1 register contains a copy of the Protection Word from Information Block 1. The Protection
Word is sampled at reset. The contents of the FMAR1 register define the current Flash memory protection
settings. The CPU bus master has read-only access to this register. The FSMAR1 register has the same
value as the FMAR1 register. The format is the same as the format of the Protection Word (see
Section 8.4.2).
15
13
12
10
9
7
6
4
3
1
0
WRPROT
RDPROT
ISPE
EMPTY
BOOTAREA
1
8.5.19 Flash Memory Auto-Read Register 2 (FMAR2/ FSMAR2)
The FMAR2 register is a word-wide read-only register, which is loaded during reset. It is used to build the
Code Area start address. At reset, the CPU executes a branch, using the contents of the FMAR2 register
as displacement. The CPU bus master has read-only access to this register.
The FSMAR2 register has the same value as the FMAR2 register.
7
0
CADR7:0
15
14
CADR15
CADR14:11
11
10
8
CADR10:8
CADR10:0
CADR14:11
CADR15
The Code Area Start Address (bits 10:0) contains the lower 11 bits of the Code Area start
address. The CADR10:0 field has a fixed value of 0.
The Code Area Start Address (bits 14:11) are loaded during reset with the inverted value
of BOOTAREA3:0.
The Code Area Start Address (bits 15) contains the upper bit of the Code Area start
address. The CADR15 field has a fixed value of 0.
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