CP3BT23_14 Datasheet, PDF (75/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
12 Power Management
The Power Management Module (PMM) improves the efficiency of the CP3BT23 by changing the
operating mode (and therefore the power consumption) according to the required level of device activity.
The device implements four power modes:
• Active
• Power Save
• Idle
• Halt
Table 12-1 summarizes the differences between power modes: the state of the high-frequency oscillator
(on or off), the System Clock source (clock used by most modules), and the clock source used by the
Timing and Watchdog Module (TWM). The high-frequency oscillator generates the 12-MHz Main Clock,
and the low-frequency oscillator generates a 32.768 kHz clock. The Slow Clock can be driven by the
32.768 kHz clock or a scaled version of the Main Clock.
Mode
Active
Power Save
Idle
Halt
Table 12-1. Power Mode Operating Summary
High-Frequency Oscillator
On
On or Off
On or Off
Off
System Clock
Main Clock
Slow Clock
None
None
TWM Clock
Slow Clock
Slow Clock
Slow Clock
None
The low-frequency oscillator continues to operate in all four modes and power must be provided
continuously to the device power supply pins. In Halt mode, however, Slow Clock does not toggle, and as
a result, the TWM timer and Watchdog Module do not operate. For the Power Save and Idle modes, the
high-frequency oscillator can be turned on or off under software control, as long as the low-frequency
oscillator is used to drive Slow Clock.
Table 12-2 shows the clock sources used by the CP3BT23 device modules and their behavior in each
power mode.
Module
CPU
MIWU
PMM
TWM
Bluetooth
AAI
CVSD/PCM
ADC
All Others
Active
On
On
On
On
On/Off
On/Off
On/Off
On/Off
On/Off
Table 12-2. Module Activity Summary
Power Mode
Power Save
Idle
On/Off
Off
On
Active
On
On
On
On
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Off
Halt
Off
Active
Active
Off
Off
Off
Off
Off*
Off
Clock Source
System
System
Slow Clock
Slow Clock
Aux 1 Clock
Aux 1 Clock
Aux 2 Clock
Aux 2 Clock
System
The Analog/Digital Converter (ADC) module is not automatically disabled by entering Halt mode, however
its clock is stopped so no conversions may be performed in Halt mode. For maximum power savings,
software must disable the ADC module before entering Halt mode.
A module shown as On/Off in Table 12-2 may be enabled or disabled by software. A module shown as
Active continues to operate even while its clock is suspended, which allows wake-up events to be
processed during Idle and Halt modes.
Copyright © 2013–2014, Texas Instruments Incorporated
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