CP3BT23_14 Datasheet, PDF (148/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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18.9 MEMORY ORGANIZATION
Each CAN module occupies 144 words in the memory address space. This space is organized as 15
banks of 8 words per bank (plus one reserved bank) for the message buffers and 14 words (plus 2
reserved words) for control and status.
18.9.1 CPU Access to CAN Registers/Memory
All memory locations occupied by the message buffers are shared by the CPU and CAN module (dual-
ported RAM). The CAN module and the CPU normally have single-cycle access to this memory. However,
if an access contention occurs, the access to the memory is blocked every cycle until the contention is
resolved. This internal access arbitration is transparent to software.
Both word and byte access to the buffer RAM are allowed. If a buffer is busy during the reception of an
object (copy process from the hidden receive buffer) or is scheduled for transmission, the CPU has no
write access to the data contents of the buffer. Write to the status/control byte and read access to the
whole buffer is always enabled.
All configuration and status registers can either be accessed by the CAN module or the CPU only. These
registers provide single-cycle word and byte access without any potential wait state.
All register descriptions within the next sections have the following layout:
15
0
Bit/Field Names
Reset Value
CPU Access (R=read only, W=Write only, R/W=Read/Write)
18.9.2 Message Buffer Organization
The message buffers are the communication interfaces between CAN and the CPU for the transmission
and the reception of CAN frames. There are 15 message buffers located at fixed addresses in the RAM
location. As shown in Table 18-7, each buffer consists of two words reserved for the identifiers, 4 words
reserved for up to eight CAN data bytes, one word reserved for the time stamp, and one word for data
length code, transmit priority code, and the buffer status codes.
Table 18-7. Message Buffer Map
Address
0E
F0XEh
0E
F0XCh
0E
F0XAh
0E
F0X8h
0E
F0X6h
0E
F0X4h
0E
F0X2h
0E
F0X0h
Buffer
Register
ID1
ID0
DATA0
DATA1
DATA2
DATA3
TSTP
CNSTAT
15 14 13 12 11 10 9
8
7
XI[28:18]/ID[10:0]
XI[14:0]
Data1[7:0]
Data3[7:0]
Data5[7:0]
Data7[7:0]
TSTP[15:0]
DLC
Reserved
6
5
4
3
SRR
/RTR
IDE
Data2[7:0]
Data4[7:0]
Data6[7:0]
Data8[7:0]
PRI
21
0
XI[17:15]
RTR
ST
148 CAN Module
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