CP3BT23_14 Datasheet, PDF (233/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
23.3.1 ACB Serial Data Register (ACBSDA)
The ACBSDA register is a byte-wide, read/write shift register used to transmit and receive data. The most
significant bit is transmitted (received) first and the least significant bit is transmitted (received) last.
Reading or writing to the ACBSDA register is allowed when ACBST.SDAST is set; or for repeated starts
after setting the START bit. An attempt to access the register in other cases produces unpredictable
results.
7
0
DATA
23.3.2 ACB Status Register (ACBST)
The ACBST register is a byte-wide, read-only register that maintains current ACB status. When reset,
disabled, or in Halt or Idle modes, ACBST is cleared.
7
SLVSTP
6
SDAST
5
BER
4
NEGACK
3
STASTR
2
NMATCH
1
MASTER
0
XMIT
XMIT
The Direction Bit bit is set when the ACB module is currently in master/slave transmit mode.
Otherwise it is cleared.
0 – Receive mode.
1 – Transmit mode.
MASTER
The Master bit indicates that the module is currently in master mode. It is set when a request
for bus mastership succeeds. It is cleared upon arbitration loss (BER is set) or the
recognition of a Stop Condition.
0 – Slave mode.
1 – Master mode.
NMATCH
The New match bit is set when the address byte following a Start Condition, or repeated
starts, causes a match or a global-call match. The NMATCH bit is cleared when written with
1. Writing 0 to NMATCH is ignored. If the ACBCTL1.INTEN bit is set, an interrupt is sent
when this bit is set.
0 – No match.
1 – Match or global-call match.
STASTR
The Stall After Start bit is set by the successful completion of an address sending (i.e., a
Start Condition sent without a bus error, or negative acknowledge), if the
ACBCTL1.STASTRE bit is set. This bit is ignored in slave mode. When the STASTR bit is
set, it stalls the bus by pulling down the SCL line, and suspends any other action on the bus
(e.g., receives first byte in master receive mode). In addition, if the ACBCTL1.INTEN bit is
set, it also sends an interrupt to the core. Writing 1 to the STASTR bit clears it. It is also
cleared when the module is disabled. Writing 0 to the STASTR bit has no effect.
0 – No stall after start condition.
1 – Stall after successful start.
NEGACK
The Negative Acknowledge bit is set by hardware when a transmission is not acknowledged
on the ninth clock. (In this case, the SDAST bit is not set.) Writing 1 to NEGACK clears it. It
is also cleared when the module is disabled. Writing 0 to the NEGACK bit is ignored.
0 – No transmission not acknowledged condition.
1 – Transmission not acknowledged.
BER
The Bus Error bit is set by the hardware when a Start or Stop Condition is detected during
data transfer (i.e., Start or Stop Condition during the transfer of bits 2 through 8 and
acknowledge cycle), or when an arbitration problem is detected. Writing 1 to the BER bit
clears it. It is also cleared when the module is disabled. Writing 0 to the BER bit is ignored.
0 – No bus error occurred.
1 – Bus error occurred.
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