CP3BT23_14 Datasheet, PDF (20/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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5.4 CONFIGURATION REGISTER (CFG)
The CFG register is used to enable or disable various operating modes and to control optional on-chip
caches. Because the CP3BT23 does not have cache memory, the cache control bits in the CFG register
are reserved. All CFG bits are cleared on reset.
15
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
I
P
E
O
N
Z
F
O
U
L
T
C
ED The Extended Dispatch bit selects whether the size of an entry in the interrupt dispatch table
(IDT) is 16 or 32 bits. Each entry holds the address of the appropriate exception handler. When
the IDT has 16-bit entries, and all exception handlers must reside in the first 128K of the
address space. The location of the IDT is held in the INTBASE register, which is not affected by
the state of the ED bit.
0 – Interrupt dispatch table has 16-bit entries.
1 – Interrupt dispatch table has 32-bit entries.
SR The Short Register bit enables a compatibility mode for the CR16B large model. In the CR16C
core, registers R12, R13, and RA are extended to 32 bits. In the CR16B large model, only the
lower 16 bits of these registers are used, and these “short registers” are paired together for 32-
bit operations. In this mode, the (RA, R13) register pair is used as the extended RA register, and
address displacements relative to a single register are supported with offsets of 0 and 14 bits in
place of the index addressing with these displacements.
0 – 32-bit registers are used.
1 – 16-bit registers are used (CR16B mode).
5.5 ADDRESSING MODES
The CR16C CPU core implements a load/store architecture, in which arithmetic and logical instructions
operate on register operands. Memory operands are made accessible in registers using load and store
instructions. For efficient implementation of I/O-intensive embedded applications, the architecture also
provides a set of bit operations that operate on memory operands.
The load and store instructions support these addressing modes: register/pair, immediate, relative,
absolute, and index addressing. When register pairs are used, the lower bits are in the lower index
register and the upper bits are in the higher index register. When the CFG.SR bit is clear, the 32bit
registers R12, R13, RA, and SP are also treated as register pairs.
References to register pairs in assembly language use parentheses. With a register pair, the lower
numbered register pair must be on the right. For example,
• jump (r5, r4)
• load $4(r4,r3), (r6,r5)
• load $5(r12), (r13)
The instruction set supports the following addressing modes:
Register/Pair
Mode
Immediate Mode
In register/pair mode, the operand is held in a general-purpose register, or in a
general-purpose register pair. For example, the following instruction adds the
contents of the low byte of register r1 to the contents of the low byte of r2, and
places the result in the low byte register r2. The high byte of register r2 is not
modified.
ADDB R1, R2
In immediate mode, the operand is a constant value which is encoded in the
instruction. For example, the following instruction multiplies the value of r4 by 4 and
places the result in r4.
MULW $4, R4
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CPU Architecture
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