CP3BT23_14 Datasheet, PDF (169/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
19.1.5 Serial Receive Clock (SRCLK)
The SRCLK pin is a bidirectional signal that provides the receive serial shift clock in asynchronous mode.
In this mode, data is sampled on the negative edge of SRCLK. The SRCLK signal may be generated
internally or it may be provided by an external clock source. In synchronous mode, the SCK pin is used as
shift clock for both the receiver and transmitter, so the SRCLK pin is available for use as a general-
purpose port pin or an auxiliary frame sync signal to access multiple slave devices (e.g. codecs) within a
network (Network mode).
19.1.6 Serial Receive Frame Sync (SRFS)
The SRFS pin is a bidirectional signal that provides frame synchronization for the receiver in
asynchronous mode. The frame sync signal may be generated internally, or it may be provided by an
external source. In synchronous mode, the SFS signal is used as the frame sync signal for both the
transmitter and receiver, so the SRFS pin is available for use as a general-purpose port pin or an auxiliary
frame sync signal to access multiple slave devices (e.g. codecs) within a network (Network Mode).
19.2 AUDIO INTERFACE MODES
There are two clocking modes: asynchronous mode and synchronous mode. These modes differ in the
source and timing of the clock signals used to transfer data. When the AAI is generating the bit shift clock
and frame sync signals internally, synchronous mode must be used.
There are two framing modes: normal mode and network mode. In normal mode, one word is transferred
per frame. In network mode, up to four words are transferred per frame. A word may be 8 or 16 bits. The
part of the frame which carries a word is called a slot. Network mode supports multiple external devices
sharing the interface, in which each device is assigned its own slot. Separate frame sync signals are
provided, so that each device is triggered to send or receive its data during its assigned slot.
19.2.1 Asynchronous Mode
In asynchronous mode, the receive and transmit paths of the audio interface operate independently, with
each path using its own bit clock and frame sync signal. Independent clocks for receive and transmit are
only used when the bit clock and frame sync signal are supplied externally. If the bit clock and frame sync
signals are generated internally, both paths derive their clocks from the same set of clock prescalers.
19.2.2 Synchronous Mode
In synchronous mode, the receive and transmit paths of the audio interface use the same shift clock and
frame sync signal. The bit shift clock and frame sync signal for both paths are derived from the same set
of clock prescalers.
19.2.3 Normal Mode
In normal mode, each rising edge on the frame sync signal marks the beginning of a new frame and also
the beginning of a new slot. A slot does not necessarily occupy the entire frame. (A frame can be longer
than the data word transmitted after the frame sync pulse.) Typically, a codec starts transmitting a fixed
length data word (e.g. 8-bit log PCM data) with the frame sync signal, then the codec’s transmit pin
returns to the high-impedance state for the remainder of the frame.
The Audio Receive Shift Register (ARSR) de-serializes received on the SRD pin (serial receiver data).
Only the data sampled after the frame sync signal are treated as valid. If the interface is interrupt-driven,
valid data bits are transferred from the ARSR to the receive FIFO. If the interface is configured for DMA,
the data is transferred to the receive DMA register 0 (ARDR0).
The serial transmit data (STD) pin is only an active output while data is shifted out. After the defined
number of data bits have been shifted out, the STD pin returns to the highimpedance state.
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