CP3BT23_14 Datasheet, PDF (235/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
TSDA
TGSCL
The Test SDA bit samples the state of the SDA signal. This bit can be used while recovering
from an error condition in which the SDA signal is constantly pulled low by a slave that went
out of sync. This bit is a read-only bit. Data written to it is ignored.
The Toggle SCL bit enables toggling the SCL signal during error recovery. When the SDA
signal is low, writing 1 to this bit drives the SCL signal high for one cycle. Writing 1 to TGSCL
when the SDA signal is high is ignored. The bit is cleared when the clock toggle is
completed.
0 – Writing 0 has no effect. 1
– Writing 1 toggles the SDA signal high for one cycle.
23.3.4 ACB Control Register 1 (ACBCTL1)
The ACBCTL1 register is a byte-wide, read/write register that configures and controls the ACB module.
When reset, disabled, or in Halt or Idle modes, the ACBCTL1 register is cleared.
7
STASTRE
6
NMINTE
5
GCMEN
4
ACK
3
2
1
0
Res
INTEN
STOP
START
START
STOP
INTEN
ACK
The Start bit is set to generate a Start Condition on the ACCESS.bus. The START bit is
cleared when the Start Condition is sent, or upon detection of a Bus Error (ACBST.BER =
1). This bit should be set only when in Master mode, or when requesting Master mode. If
this device is not the active master of the bus (ACBST.MASTER = 0), setting the START bit
generates a Start Con0dition as soon as the ACCESS.bus is free (ACBCST.BB = 0). An
address send sequence should then be performed. If this device is the active master of the
bus (ACBST.MASTER = 1), when the START bit is set, a write to the ACBSDA register
generates a Start Condition, then the ACBSDA data is transmitted as the slave’s address
and the requested transfer direction. This case is a repeated Start Condition. It may be used
to switch the direction of the data flow between the master and the slave, or to choose
another slave device without using a Stop Condition in between.
0 – Writing 0 has no effect.
1 – Writing 1 generates a Start condition.
The Stop bit in master mode generates a Stop Condition that completes or aborts the
current message transfer. This bit clears itself after the Stop condition is issued.
0 – Writing 0 has no effect.
1 – Writing 1 generates a Stop condition.
The Interrupt Enable bit controls generating ACB interrupts. When the INTEN bit is cleared
ACB interrupt is disabled. When the INTEN bit is set, interrupts are enabled.
0 – ACB interrupts disabled.
1 – ACB interrupts enabled. An interrupt is generated (the interrupt signals to the ICU is
high) on any of the following events:
• An address MATCH is detected (ACBST.NMATCH = 1) and the NMINTE bit is set.
• A Bus Error occurs (ACBST.BERR = 1).
• Negative acknowledge after sending a byte (ACBST.NEGACK = 1).
• An interrupt is generated on acknowledge of each transaction (same as hardware setting
the ACBST.SDAST bit).
• If ACBCTL1.STASTRE = 1, in master mode after a successful start (ACBST.STASTR =
1).
• Detection of a Stop Condition while in slave receive mode (ACBST.SLVSTP = 1).
The Acknowledge bit holds the value this device sends in master or slave mode during the
next acknowledge cycle. Setting this bit to 1 instructs the transmitting device to stop sending
data, since the receiver either does not need, or cannot receive, any more data. This bit is
cleared after the first acknowledge cycle. This bit is ignored when in transmit mode
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ACCESS.bus Interface 235