CP3BT23_14 Datasheet, PDF (100/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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Write Operation
When the R/W bit is clear, the 16 bits of the data field are shifted out of the CP3BT23 on the falling edge
of SCLK. Data is sampled by the radio chip on the rising edge of SCLK. When SLE is high, the 16-bit data
are copied into the radio chip register on the next rising edge of SCLK. The data is loaded in the
appropriate radio chip register depending on the state of the four address bits, Address[4:0]. Figure 15-3
shows the timing for the write operation.
Figure 15-3. Serial Interface Write Timing
Read Operation
When the R/W bit is set, data is shifted out of the radio chip on the rising edge of SCLK. Data is sampled
by the CP3BT23 on the falling edge of SCLK. On reception of the read command (R/W = 1), the radio chip
takes control of the Figure 15-5. Serial Interface 16-bit Fast-Write Timing serial interface data line. The
received 16-bit data is loaded by the CP3BT23 after the first falling edge of SCLK when SLE is high.
When SLE is high, the radio chip releases the SDAT line again on the next rising edge of SCLK. The
CP3BT23 takes control of the SDAT line again after the following rising edge of SCLK. Which radio chip
register is read, depends on the state of the four address bits, Address[4:0]. The transfer is always 16 bits,
without regard to the actual size of the register. Unimplemented bits contain undefined data. Figure 15-4
shows the timing for the read operation.
Figure 15-4. Serial Interface Read Timing
100 Bluetooth Controller
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