CP3BT23_14 Datasheet, PDF (102/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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32-Bit Write Operation
On the LMX5252, a 32-bit register is loaded by writing to the same register address twice. The first write
loads the high word (bits 31:16), and the second write loads the low word (bits 15:0). The two writes must
be separated by at least two clock cycles. For a 4-MHz clock, the minimum separation time is 500 ns.
The value read from a 32-bit register is a counter value, not the contents of the register. The counter value
indicates which words have been written. If the high word has been written, the counter reads as 0000h. If
both words have been written, the counter reads as 0001h. The value returned by reading a 32-bit register
is independent of the contents of the register.
Figure 15-7 and Figure 15-8 show the timing for 32-bit register writing and reading.
The order for accessing the registers is from high to low: 17, 15, 14, 12, 11, 10, 9, 8, 7, 6, 5, 4, 2, and 1.
These registers must be written during the initialization of the LMX5252.
Figure 15-7. 32-Bit Write Timing
SDAT
H2 H1 H0 R A4 A3 A2 A1 A0 D31
D16
H2 H1 H0 R A4 A3 A2 A1 A0 D15
D0
SCLK
>500 ns
SLE
DS323
Figure 15-8. 32-Bit Read Timing
An example of a 32-bit write is shown in Table 15-1. In this example, the 32-bit value FFFF DC04h is
written to register address 0Ah. In cycle 1, the high word (FFFFh) is written. In the first part of cycle 2, the
CP3BT23 drives the header, R/ W bit, and register address for a read cycle. In the second part of cycle 2,
the LMX5252 drives the counter value. The counter value is 0, which indicates one word has been written.
In cycle 3, the low word (DC04h) is written. In the first part of cycle 4, the CP3BT23 drives the header,
R/W bit, and register address for a read cycle. In the second part of cycle 4, the LMX5252 drives the
counter value. The counter value is 1, which indicates two words have been written
Table 15-1. Example of 32-Bit Write with Interleaved Reads
Cycle
1
2
3
4
Serial Data on SDAT
Description
101 0 01010 1111111111111111
Write cycle driven by CP3BT23. Data is FFFFh. Address is 0Ah.
101 1 01010
First part of read cycle driven by CP3BT23. Address is 0Ah.
0000000000000000 Second part of read cycle driven by LMX5252. Counter value is 0.
101 0 01010 1101110000000100
Write cycle driven by CP3BT23. Data is DC04h. Address is 0Ah.
101 1 01010
First part of read cycle driven by CP3BT23. Address is 0Ah.
0000000000000001 Second part of read cycle driven by LMX5252. Counter value is 1.
102 Bluetooth Controller
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