CP3BT23_14 Datasheet, PDF (36/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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8 Flash Memory
The flash memory consists of the flash program memory and the flash data memory. The flash program
memory is further divided into the Boot Area and the Code Area.
A special protection scheme is applied to the lower portion of the flash program memory, called the Boot
Area. The Boot Area always starts at address 0 and ranges up to a programmable end address. The
maximum boot area address which can be selected is 00 77FFh. The intended use of this area is to hold
In-System-Programming (ISP) routines or essential application routines. The Boot Area is always
protected against CPU write access, to avoid unintended modifications.
The Code Area is intended to hold the application code and constant data. The Code Area begins with the
next byte after the Boot Area. Table 8-1 summarizes the properties of the regions of flash memory
mapped into the CPU address space.
Area
Boot Area
Code Area
Data Area
Table 8-1. Flash Memory Areas
Address Range
0–BOOTAREA 1
BOOTAREA–03 FFFFh
0D 0000h–0D 1FFFh
Read Access
Yes
Yes
Yes
Write Access
No
Write access only if section write enable bit is set and
global write protection is disabled.
Write access only if section write enable bit is set and
global write protection is disabled.
8.1 FLASH MEMORY PROTECTION
The memory protection mechanisms provide both global and section-level protection. Section-level
protection against CPU writes is applied to individual 8K-byte sections of the flash program memory and
512-byte sections of the flash data memory. Section-level protection is controlled through read/write
registers mapped into the CPU address space. Global write protection is applied at the device level, to
disable flash memory writes by the CPU. Global write protection is controlled by the encoding of bits
stored in the flash memory array.
8.1.1 Section-Level Protection
Each bit in the Flash Memory Write Enable (FM0WER and FM1WER) registers enables or disables write
access to a corresponding section of flash program memory. Write access to the flash data memory is
controlled by the bits in the Flash Slave Memory Write Enable (FSM0WER) register. By default (after
reset) all bits in the FM0WER, FM1WER, and FSM0WER registers are cleared, which disables write
access by the CPU to all sections. Write access to a section is enabled by setting the corresponding write
enable bit. After completing a programming or erase operation, software should clear all write enable bits
to protect the flash program memory against any unintended writes.
8.1.2 Global Protection
The WRPROT field in the Protection Word controls global write protection. The Protection Word is located
in a special flash memory outside of the CPU address space. If a majority of the bits in the 3-bit WRPROT
field are clear, write protection is enabled. Enabling this mode prevents the CPU from writing to flash
memory.
The RDPROT field in the Protection Word controls global read protection. If a majority of the bits in the 3-
bit RDPROT field are clear, read protection is enabled. Enabling this mode prevents reading by an
external debugger through the serial debug interface or by an external flash programmer. CPU read
access is not affected by the RDPROT bits.
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Flash Memory
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