CP3BT23_14 Datasheet, PDF (293/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
29.9 OUTPUT SIGNAL LEVELS
All output signals are powered by the digital supply (VCC). Table 29-1 summarizes the states of the output
signals during the reset state (when VCC power exists in the reset state) and during the Power Save
mode.
The RESET and NMI input pins are active during the Power Save mode. In order to guarantee that the
Power Save current not exceed 1 mA, these inputs must be driven to a voltage lower than 0.5V or higher
than VCC 0.5V. An input voltage between 0.5V and (VCC 0.5V) may result in power consumption
exceeding 1 mA.
Signals on a Pin
PB7:0
PC7:0
PE5:0
PF7:0
PG7:0
PH7:0
PJ7:0
Table 29-1. Output Pins During Reset and Power-Save
Reset State (with Vcc)
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
Power Save Mode
Previous state
Previous state
Previous state
Previous state
Previous state
Previous state
Previous state
Comments
I/O ports will maintain their values when
entering power-save mode
29.10 CLOCK AND RESET TIMING
(Specified by design. All timing except memory interface characterized not tested for production.)
Table 29-2. Clock and Reset Signals
Symbol
Figure
Description
Reference
Min (ns)
Max (ns)
Clock Input Signals
t_X1p
Figure 29-1 X1 period
Rising Edge (RE) on X1 to next RE on
X1
83.33
83.33
t_X1h
Figure 29-1 X1 high time, external clock
At 2V level (Both Edges)
t_X1l
Figure 29-1 X1 low time, external clock
t_X2p
Figure 29-1 X2 period⁽¹⁾
At 0.8V level (Both Edges)
RE on X2 to next RE on X2
t_X2h
Figure 29-1 X2 high time, external clock
At 2V level (both edges)
t_X2l
Figure 29-1 X2 low time, external clock
At 0.8V level (both edges)
t_IH
Figure 29-2 Input hold time (NMI, RXD1, RXD2) After RE on CLK
Reset and NMI Input Signals
(0.5 Tclk) 5
–
(0.5 Tclk) 5
–
10,000
–
(0.5 Tclk) 500
–
(0.5 Tclk) 500
–
0
–
t_IW
Figure 29-2 NM Pulse Width
t_RST
Figure 29-3 RESET Pulse Width
t_R
Figure 29-3 Vcc Rise Time
Falling Edge (FE) to NMI RE
RESET FE to RE
0.1 Vcc to 0.9 Vcc
20
–
100
–
–
–
(1) Only when operating with an external square wave on X2CKI; otherwise a 32 kHz crystal network must be used between X2CKI and
X2CKO. If Slow Clock is internally generated from Main Clock, it may not exceed this given limit.
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