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| CP3BT23_14 Datasheet, PDF (35/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces | |||
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CP3BT23
www.ti.com
SNOSCX3A â JULY 2013 â REVISED JANUARY 2014
A second set of special values written to the SWRESET register will cause a reset out of ISP mode
(whether or not the device is currently in ISP mode). This can be used as a simple software reset. In this
case, no conditions are checked. To initiate reset out of ISP mode, write the value E1h to the SWRESET
register, followed within 127 clock cycles by the value 0Eh. The reset then follows immediately. This
sequence is called SWRESET(CLR). This reset also cancels the effect of any previous SWRESET(ISP),
so subsequent resets will check the EMPTY bits to determine whether to enter ISP mode.
The ISP reset behaves similarly to the Watchdog reset, for example, if the flash interface is busy when
reset is asserted, the reset to the clock module is delayed until the flash operations are completed.
Copyright © 2013â2014, Texas Instruments Incorporated
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Product Folder Links: CP3BT23
System Configuration Registers
35
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