CP3BT23_14 Datasheet, PDF (198/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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20.9.10 CVSD Status Register (CVSTAT)
The CVSTAT register is a 16-bit wide, read-only register that holds the status information of the
CVSD/PCM module. At reset, and if the CVCTL1.CVEN bit is clear, all implemented bits are cleared.
7
5
CVINST
4
CVF
3
CVE
2
PCMINT
1
CVNF
0
CVNE
15
11
10
8
Reserved
CVOUTST
CVNE
CVNF
PCMINT
CVE
CVF
CVINST
CVOUTST
The CVSD In FIFO Nearly Empty bit indicates when only three CVSD data words are left in
the CVSD In FIFO, so new CVSD data should be written into the CVSD In FIFO. If the
CVSDINT bit is set, an interrupt will be asserted when the CVNE bit is set. If the DMACI bit
is set, a DMA request will be asserted when this bit is set. The CVNE bit is cleared when
the CVSTAT register is read.
0 – CVSD In FIFO is not nearly empty.
1 – CVSD In FIFO is nearly empty.
The CVSD Out FIFO Nearly Full bit indicates when only three empty word locations are left
in the CVSD Out FIFO, so the CVSD Out FIFO should be read. If the CVSDINT bit is set,
an interrupt will be asserted when the CVNF bit is set. If the DMACO bit is set, a DMA
request will be asserted when this bit is set. Software must not rely on the CVNF bit as an
indicator of the number of valid words in the FIFO. Software must check the CVOUTST
field to read the number of valid words in the FIFO. The CVNF bit is cleared when the
CVSTAT register is read.
0 – CVSD Out FIFO is not nearly full.
1 – CVSD Out FIFO is nearly full.
The PCM Interrupt bit set indicates that the PCMOUT register is full and needs to be read
or the PCMIN register is empty and needs to be loaded with new PCM data. The PCMINT
bit is cleared when the CVSTAT register is read, unless the device is in FREEZE mode.
0 – PCM does not require service.
1 – PCM requires loading or unloading.
The CVSD In FIFO Empty bit indicates when the CVSD In FIFO has been read by the
CVSD converter while the FIFO was already empty. If the CVSDERRORINT bit is set, an
interrupt will be asserted when the CVE bit is set. The CVE bit is cleared when the
CVSTAT register is read, unless the device is in FREEZE mode.
0 – CVSD In FIFO has not been read while empty.
1 – CVSD In FIFO has been read while empty.
The CVSD Out FIFO Full bit set indicates whether the CVSD Out FIFO has been written by
the CVSD converter while the FIFO was already full. If the CVSDERRORINT bit is set, an
interrupt will be asserted when the CVF bit is set. The CVF bit is cleared when the
CVSTAT register is read, unless the device is in FREEZE mode.
0 – CVSD Out FIFO has not been written while full.
1 – CVSD Out FIFO has been written while full.
The CVSD In FIFO Status field reports the current number of empty 16-bit word locations
in the CVSD In FIFO. When the FIFO is empty, the CVINST field will read as 111b. When
the FIFO holds 7 or 8 words of data, the CVINST field will read as 000b.
CVSD Out FIFO Status field reports the current number of valid 16-bit CVSD data words in
the CVSD Out FIFO. When the FIFO is empty, the CVOUTST field will read as 000b.
When the FIFO holds 7 or 8 words of data, the CVOUTST field will read as 111b.
198 CVSD/PCM Conversion Module
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