CP3BT23_14 Datasheet, PDF (60/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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10.3 INTERRUPT CONTROLLER REGISTERS
Table 10-1 lists the ICU registers.
Name
IVCT
NMISTAT
EXNMI
ISTAT0
ISTAT1
ISTAT2
IENAM0
IENAM1
IENAM2
Table 10-1. Interrupt Controller Registers
Address
FF FE00h
FF FE02h
FF FE04h
FF FE0Ah
FF FE0Ch
FF FE20h
FF FE0Eh
FF FE10h
FF FE22h
Description
Interrupt Vector Register
Non-Maskable Interrupt Status Register
External NMI Trap Control and Status Register
Interrupt Status Register 0
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Enable and Mask Register 0
Interrupt Enable and Mask Register 1
Interrupt Enable and Mask Register 2
10.3.1 Interrupt Vector Register (IVCT)
The IVCT register is a byte-wide read-only register which reports the encoded value of the highest priority
maskable interrupt that is both asserted and enabled. The valid range is from 10h to 3Fh. The register is
read by the CPU during an interrupt acknowledge bus cycle, and INTVECT is valid during that time. It may
contain invalid data while INTVECT is updated.
7
6
5
0
0
0
INTVECT
INTVECT The Interrupt Vector field indicates the highest priority interrupt which is both asserted and
enabled.
10.3.2 Non-Maskable Interrupt Status Register (NMISTAT)
The NMISTAT register is a byte-wide read-only register. It holds the status of the current pending Non-
Maskable Interrupt (NMI) requests. On the CP3BT23, the external NMI input is the only source of NMI
interrupts. The NMISTAT register is cleared on reset and each time its contents are read.
7
1
0
Reserved
EXT
EXT
The External NMI request bit indicates whether an external non-maskable interrupt request
has occurred. Refer to the description of the EXNMI register below for additional details.
0 – No external NMI request.
1 – External NMI request has occurred.
60
Interrupts
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