CP3BT23_14 Datasheet, PDF (42/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
EMPTY
Not Empty
Table 8-6. CPU Reset Behavior
ISPE
Boot Area
ISP
Defined
Not Empty
ISP
Not Defined
Not Empty
No ISP
Don’t Care
Empty
Empty
Empty
ISP
ISP
No ISP
Defined
Not Defined
Don’t Care
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Start-Up Operation
Device starts in IRE/ ERE mode from
Code Area start address
Device starts in IRE/ ERE mode from
Code Area start address
Device starts in IRE/ ERE mode from
address 0
Device starts in ISP mode from Code
Area start address
Device starts in ISP mode and is kept
in its reset state
RDPROT
WRPROT
The RDPROT field controls the global read protection mechanism for the on-chip flash
program memory. If a majority of the three RDPROT bits are clear, the flash program
memory is protected against read access from the serial debug interface or an external
flash programmer. CPU read access is not affected by the RDPROT bits. If a majority of the
RDPROT bits are set, read access is allowed.
The WRPROT field controls the global write protection mechanism for the on-chip flash
program memory. If a majority of the three WRPROT bits are clear, the flash program
memory is protected against write access from any source and read access from the serial
debug interface. If a majority of the WRPROT bits are set, write access is allowed.
8.5 FLASH MEMORY INTERFACE REGISTERS
There is a separate interface for the program flash and data flash memories. The same set of registers
exist in both interfaces. In most cases they are independent of each other, but in some cases the program
flash interface controls the interface for both memories, as indicated in the following sections. Table 8-7
lists the registers.
Program Memory
FMIBAR FF F940h
FMIBDR FF F942h
FM0WER FF F944h
FM1WER FF F946h
FMCTRL FF F94Ch
FMSTAT FF F94Eh
FMPSR FF F950h
FMSTART FF F952h
FMTRAN FF F954h
FMPROG FF F956h
FMPERASE FF F958h
FMMERASE0 FF F95Ah
FMEND FF F95Eh
FMMEND FF F960h
FMRCV FF F962h
FMAR0 FF F964h
FMAR1 FF F966h
FMAR2 FF F968h
Table 8-7. Flash Memory Interface Registers
Data Memory
FSMIBAR FF F740h
FSMIBDR FF F742h
FSM0WER FF F744h
N/A
FSMCTRL FF F74Ch
FSMSTAT FF F74Eh
FSMPSR FF F750h
FSMSTART FF F752h
FSMTRAN FF F754h
FSMPROG FF F756h
FSMPERASE FF F758h
FSMMERASE0 FF F75Ah
FSMEND FF F75Eh
FSMMEND FF F760h
FSMRCV FF F762h
FSMAR0 FF F764h
FSMAR1 FF F766h
FSMAR2 FF F768h
Description
Flash Memory Information Block Address Register
Flash Memory Information Block Address Register
Flash Memory 0 Write Enable Register
Flash Memory 1 Write Enable Register
Flash Memory Control Register
Flash Memory Status Register
Flash Memory Prescaler Register
Flash Memory Start Time Reload Register
Flash Memory Transition Time Reload Register
Flash Memory Programming Time Reload Register
Flash Memory Page Erase Time Reload Register
Flash Memory Module Erase Time Reload Register 0
Flash Memory End Time Reload Register
Flash Memory Module Erase End Time Reload
Register
Flash Memory Recovery Time Reload Register
Flash Memory Auto-Read Register 0
Flash Memory Auto-Read Register 1
Flash Memory Auto-Read Register 2
42
Flash Memory
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