CP3BT23_14 Datasheet, PDF (65/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
11 Triple Clock and Reset
The Triple Clock and Reset module generates a 12 MHz Main Clock and a 32.768 kHz Slow Clock from
external crystal networks or external clock sources. It provides various clock signals for the rest of the
chip. It also provides the main system reset signal, a power-on reset function, Main Clock prescalers to
generate two additional low-speed clocks, and a 32-kHz oscillator start-up delay.
Figure 11-1 is block diagram of the Triple Clock and Reset module.
Reset
TWM (Invalid Watchdog Service)
Flash Interface (Program/Erase Busy)
External Reset
Power-On-Reset
Module (POR)
Reset
Module
Device Reset
Stretched
Reset
Stop Main Osc.
X1CKI
X1CKO
High Frequency
Oscillator
Preset
Start-Up-Delay
14-Bit Timer
4-Bit Aux1
Prescaler
4-Bit Aux2
Prescaler
Main Clock
X2CKI
Low Frequency
Oscillator
X2CKO
Div.
8-Bit
by 2
Prescaler
Slow Clock Prescaler
Start-Up-Delay
8-Bit Timer
Preset
Time-out
Fast Clock
Prescaler
4-Bit
Prescaler
Stop Main Osc
Good Main Clock
Auxiliary Clock 1
Auxiliary Clock 2
Slow Clock
Slow Clock
Select
Good Slow Clock
Stop Slow Osc
Bypass
32 kHz Osc
System Clock
Fast Clock
Select
PLL
(x3, x4, or x5)
Stop PLL
PLL Clock
Bypass PLL
Good PLL Clock
Stop PLL
DS006
Figure 11-1. Triple Clock and Reset Module
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Triple Clock and Reset
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