CP3BT23_14 Datasheet, PDF (56/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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9.6.3 Device B Address Counter Register (ADCBn)
The Device B Address Counter register is a 32-bit, read/ write register. It holds the current 24-bit address
of either the source data item, or the destination location, according to the DIR bit in the CNTLn register.
The ADCBn register is updated after each transfer cycle by INCB field of the DMACNTLn register
according to ADB bit of the DMACNTLn register. In direct (flyby) mode, this register is not used. The
upper 8 bits of the ADCBn register are reserved and always clear.
31
24
23
0
Reserved
Device B Address Counter
9.6.4 Device B Address Register (ADRBn)
The Device B Address register is a 32-bit, read/write register. It holds the 24-bit starting address of either
the next source data block or the next destination data area, according to the DIR bit in the CNTLn
register. In direct (flyby) mode, this register is not used. The upper 8 bits of the ADCRBn register are
reserved and always clear.
31
24
23
0
Reserved
Device B Address
9.6.5 Block Length Counter Register (BLTCn)
The Block Length Counter register is a 16-bit, read/write register. It holds the current number of DMA
transfers to be executed in the current block. BLTCn is decremented by one after each transfer cycle. A
DMA transfer may consist of 1 or 2 bytes, as selected by the DMACNTLn.TCS bit.
15
0
Block Length Counter
Note: 0000h is interpreted as 2¹⁶-1 transfer cycles.
9.6.6 Block Length Register (BLTRn)
The Block Length register is a 16-bit, read/write register. It holds the number of DMA transfers to be
performed for the next block. Writing this register automatically sets the DMASTAT.VLD bit.
15
0
Block Length
Note: 0000h is interpreted as 216-1 transfer cycles.
9.6.7 DMA Control Register (DMACNTLn)
The DMA Control register n is a word-wide, read/write register that controls the operation of DMA channel
n. This register is cleared at reset. Reserved bits must be written with 0.
7
6
5
4
3
2
1
0
BPC
OT
DIR
IND
TCS
EOVR
ETC
CHEN
15
Res.
14
13
INCB
12
ADB
11
10
INCA
9
ADA
8
SWRQ
CHEN
The Channel Enable bit must be set to enable any DMA operation on this channel. Writing a 1 to
this bit starts a new DMA transfer even if it is currently a 1. If all DMACNTLn.CHEN bits are
clear, the DMA clock is disabled to reduce power.
0 – Channel disabled.
1 – Channel enabled.
56
DMA Controller
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