CP3BT23_14 Datasheet, PDF (72/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
11.9 Clock and Reset Registers
Name
CRCTRL
PRSFC
PRSSC
PRSAC
Table 11-3. Clock and Reset Registers
Address
FC40h
FF FC42h
FF FC44h
FF FC46h
Description
Clock and Reset Control Register
High Frequency Clock Prescaler Register
Low Frequency Clock Prescaler Register
Auxiliary Clock Prescaler Register
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11.9.1 Clock and Reset Control Register (CRCTRL)
The CRCTRL register is a byte-wide read/write register that controls the clock selection and contains the
power-on reset status bit. At reset, the CRCTRL register is initialized as described below:
7
6
Reserved
5
POR
4
ACE2
3
ACE1
2
PLLPWD
1
FCLK
0
SCLK
SCLK
FCLK
PLLPWD
ACE1
ACE2
The Slow Clock Select bit controls the clock source used for the Slow Clock.
0 – Slow Clock driven by prescaled Main Clock.
1 – Slow Clock driven by 32.768 kHz oscillator.
The Fast Clock Select bit selects between the 12 MHz Main Clock and the PLL as the
source used for the System Clock. After reset, the Main Clock is selected. Attempting to
switch to the PLL while the PLLPWD bit is set (PLL is turned off) is ignored. Attempting to
switch to the PLL also has no effect if the PLL output clock has not stabilized.
0 – The System Clock prescaler is driven by the output of the PLL.
1 – The System Clock prescaler is driven by the 12-MHz Main Clock. This is the default
after reset.
The PLL Power-Down bit controls whether the PLL is active or powered down (Stop PLL
signal asserted). When this bit is set, the on-chip PLL stays powered-down. Otherwise it is
powered-up or it can be controlled by the Power Management Module, respectively. Before
software can power-down the PLL in Active mode by setting the PLLPWD bit, the FCLK bit
must be set. Attempting to set the PLLPWD bit while the FCLK bit is clear is ignored. The
FCLK bit cannot be cleared until the PLL clock has stabilized. After reset this bit is set.
0 – PLL is active.
1 – PLL is powered down.
When the Auxiliary Clock Enable bit is set and a stable Main Clock is provided, the Auxiliary
Clock 1 prescaler is enabled and generates the first Auxiliary Clock. When the ACE1 bit is
clear or the Main Clock is not stable, Auxiliary Clock 1 is stopped. Auxiliary Clock 1 is used
as the clock input for the Bluetooth LLC and the Advanced Audio Interface. After reset this
bit is clear.
0 – Auxiliary Clock 1 is stopped.
1 – Auxiliary Clock 1 is active if the Main Clock is stable.
When the Auxiliary Clock Enable 2 bit is set and a stable Main Clock is provided, the
Auxiliary Clock 2 prescaler is enabled and generates Auxiliary Clock 2. When the ACE2 bit
is clear or the Main Clock is not stable, the Auxiliary Clock 2 is stopped. Auxiliary Clock 2 is
used as the clock input for the CVSD/PCM transcoder and the A/D converter. After reset
this bit is clear.
0 – Auxiliary Clock 2 is stopped.
1 – Auxiliary Clock 2 is active if the Main Clock is stable.
72
Triple Clock and Reset
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