CP3BT23_14 Datasheet, PDF (146/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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18.7 INTERRUPTS
The CAN module has one dedicated ICU interrupt vector for all interrupt conditions. In addition, the data
frame receive event is an input to the MIWU (see Section 13). The interrupt process can be initiated from
the following sources.
CAN data transfer —
• Reception of a valid data frame in the buffer. (Buffer state changes from RX_READY to RX_FULL or
RX_OVERRUN).
• Successful transmission of a data frame. (Buffer state changes from TX_ONCE to TX_NOT_ACTIVE
or RX_READY).
• Success response to a remote frame (buffer state changes from TX_ONCE_RTR to TX_RTR.)
• Transmit scheduling. (Buffer state changes from TX_RTR to TX_ONCE_RTR).
• CAN error conditions — Detection of an CAN error. (The CEIPND bit in the CIPND register will be set
as well as the corresponding bits in the error diagnostic register CEDIAG).
The receive/transmit interrupt access to every message buffer can be individually enabled/disabled in the
CIEN register. The pending flags of the message buffer are located in the CIPND register (read only) and
can be cleared by resetting the flags in the CICLR registers.
18.7.1 Highest Priority Interrupt Code
To reduce the decoding time for the CIPND register, the buffer interrupt request with the highest priority is
placed as interrupt status code into the IST[3:0] section of the CSTPND register.
Each of the buffer interrupts as well as the error interrupt can be individually enabled or disabled in the
CAN Interrupt Enable register (CIEN). As soon as an interrupt condition occurs, every interrupt request is
indicated by a flag in the CAN Interrupt Pending register (CIPND). When the interrupt code logic for the
present highest priority interrupt request is enabled, this interrupt will be translated into the IST3:0 bits of
the CAN Status Pending register (CSTPND). An interrupt request can be cleared by setting the
corresponding bit in the CAN Interrupt Clear register (CICLR).
Figure 18-26 shows the CAN interrupt management.
CIEN
CICLR
CIPND
Clear interrupt flags of every
message buffer individually
CICEN
ICODE
IRQ IST3 IST2 IST1 IST0
DS043
Figure 18-26. Interrupt Management
The highest priority interrupt source is translated into the bits IRQ and IST3:0 as shown in Table 18-6.
146 CAN Module
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