CP3BT23_14 Datasheet, PDF (171/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Network Mode
In network mode, each frame is composed of multiple slots. Each slot may transfer 8 or 16 bits. All of the
slots in a frame must have the same length. In network mode, the sync signal marks the beginning of a
new frame. Only frames with up to four slots are supported by this audio interface.
More than two devices can communicate within a network using the same clock and data lines. The
devices connected to the same bus use a time-multiplexed approach to share access to the bus. Each
device has certain slots assigned to it, in which only that device is allowed to transfer data. One master
device provides the bit clock and the frame sync signal(s). On all other (slave) devices, the bit clock and
frame sync pins are inputs.
Up to four slots can be assigned to the interface, as it supports up to four slots per frame. Any other slots
within the frame are reserved for other devices.
The transmitter only drives data on the STD pin during slots which have been assigned to this interface.
During all other slots, the STD output is in high-impedance mode, and data can be driven by other
devices. The assignment of slots to the transmitter is specified by the Transmit Slot Assignment bits
(TXSA) in the ATCR register. It can also be specified whether the data to be transmitted is transferred
from the transmit FIFO or the corresponding DMA transmit register. There is one DMA transmit register
(ATDRn) for each of the maximum four data slots. Each slot can be configured independently.
On the receiver side, only the valid data bits which were received during the slots assigned to this
interface are copied into the receive FIFO or DMA registers. The assignment of slots to the receiver is
specified by the Receive Slot Assignment bits (RXSA) in the ATCR register. It can also be specified
whether the received data is copied into the receive FIFO or into the corresponding DMA receive register.
There is one DMA receive register (ARDRn) for each of the maximum four data slots. Each slot may be
configured individually.
Figure 19-3 shows the frame timing while operating in network mode with four slots per frame, slot 1
assigned to the interface, and a long frame sync interval
Long Frame Sync
(SFS/SRFS)
Shift Data
(STD/SRD)
Data
(ignored)
Data
(valid)
High-impedance
Data
(ignored)
Slot0
Slot1
Unused Slots
Frame
Figure 19-3. Network Mode Frame
DS055
IRQ Support If DMA is not enabled for a receive slot n (RXDSAn = 0), all data received in this slot is
loaded into the receive FIFO. An IRQ is asserted as soon as the number of data bytes or words in the
receive FIFO is greater than a configured warning limit.
If DMA is not enabled for a transmit slot n (TXDSAn = 0), all data to be transmitted in this slot are read
from the transmit FIFO. An IRQ is asserted as soon as the number data bytes or words available in the
transmit FIFO is equal or less than a configured warning limit.
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Advanced Audio Interface 171