CP3BT23_14 Datasheet, PDF (78/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
www.ti.com
HALT
WBPSM
DMC
DHC
HCCM
HCCH
The Halt Mode bit indicates whether the device is in Halt mode. Before entering Halt mode,
the WBPSM bit must be set. When the HALT bit is written with 1, the device enters the Halt
mode at the execution of the next WAIT instruction. When in HALT mode, the PMM stops
the System Clock and then turns off the PLL and the high-frequency oscillator. The HALT bit
can be set and cleared by software. The Halt mode is exited by a hardware wake-up event.
When this signal is set high, the oscillator is started. After the oscillator has stabilized, the
HALT bit is cleared by the hardware.
0 – Device is not in Halt mode.
1 – Device is in Halt mode.
When the Wait Before Power Save Mode bit is clear, a switch from Active mode to Power
Save mode only requires setting the PSM bit. When the WBPSM bit is set, a switch from
Active mode to Power Save, Idle, or Halt mode is performed by setting the PSM, IDLE or
HALT bit, respectively, and then executing a WAIT instruction. Also, if the DMC or DHC bits
are set, the high-frequency oscillator and PLL may be disabled only after a WAIT instruction
is executed and the Power Save, Idle, or Halt mode is entered.
0 – Mode transitions may occur immediately.
1 – Mode transitions are delayed until the next WAIT instruction is executed.
The Disable Main Clock bit may be used to disable the high-frequency oscillator in Power
Save and Idle modes. In Active mode, the high-frequency oscillator is enabled without
regard to the DMC value. In Halt mode, the high-frequency oscillator is disabled without
regard to the DMC value. The DMC bit is cleared by hardware when a hardware wakeup
event is detected.
0 – High-frequency oscillator is only disabled in Halt mode or when disabled by the HCC
mechanism.
1 – High-frequency oscillator is also disabled in Power Save and Idle modes.
The Disable High-Frequency (PLL) Clock bit and the CRCTRL.PLLPWD bit may be used to
disable the PLL in Power Save and Idle modes. When the DHC bit is clear (and PLLPWD =
0), the PLL is enabled in these modes. If the DHC bit is set, the PLL is disabled in Power
Save and Idle mode. In Active mode with the CRCTRL.PLLPWD bit set, the PLL is enabled
without regard to the DHC value. In Halt mode, the PLL is disabled without regard to the
DMC value. The DHC bit is cleared by hardware when a hardware wake-up event is
detected.
0 – PLL is disabled only by entering Halt mode or setting the CRCTRL.PLLPWD bit.
1 – PLL is also disabled in Power Save or Idle mode.
The Hardware Clock Control for Main Clock bit may be used in Power Save and Idle modes
to disable the high-frequency oscillator conditionally, depending on whether the Bluetooth
LLC is in Sleep mode. The DMC bit must be clear for this mechanism to operate. The
HCCM bit is automatically cleared when the device enters Active mode.
0 – High-frequency oscillator is disabled in Power Save or Idle mode only if the DMC bit is
set.
1 – High-frequency oscillator is also disabled if the Bluetooth LLC is idle.
The Hardware Clock Control for High-Frequency (PLL) bit may be used in Power Save and
Idle modes to disable the PLL conditionally, depending on whether the Bluetooth LLC is in
Sleep mode. The DHC bit and the CRCTRL.PLLPWD bit must be clear for this mechanism
to operate. The HCCH bit is automatically cleared when the device enters Active mode.
0 – PLL is disabled in Power Save or Idle mode only if the DMC bit or the
CRCTRL.PLLPWD bit is set.
1 – PLL is also disabled if the Bluetooth LLC is idle.
78
Power Management
Submit Documentation Feedback
Product Folder Links: CP3BT23
Copyright © 2013–2014, Texas Instruments Incorporated