CP3BT23_14 Datasheet, PDF (119/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

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PEN_DOWN
ADC_OFLW
ADC_DONE
CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
The Pen-Down bit indicates whether a pendown condition is being sensed. To enable
pen-down detection, the TOUCH_CFG field of the ADCGCR register must be loaded
with 101b. The sense of the PEN_DOWN bit is inverted, so when pen-down detection
is enabled and a pen-down condition is sensed, the PEN_DOWN bit is clear. This bit is
not carried through the FIFO, so its value represents the current status of the pen-
down detector. When pen-down detection is enabled, the uninverted signal from the
pen-down detector is ORed with the Done signal to generate the wake-up signal
(WUI30) passed to the MIWU unit. If pen-down detection is not enabled, this bit reads
as 0.
0 – Pen-down condition is sensed, or pendown detection is disabled.
1 – No pen-down condition is sensed.
The ADC FIFO Overflow bit indicates whether the 4-word FIFO behind the ADCRESLT
register has overflowed. When this occurs, the most recent conversion result is lost.
This bit is cleared when the ADCRESLT register is read.
0 – FIFO overflow has not occurred.
1 – FIFO overflow has occurred.
The ADC Done bit indicates when an ADC conversion has completed. When this bit is
set, the data in the ADC_RESULT field is valid. When this bit is clear, there is no valid
data in the ADC_RESULT field. The Done bit is cleared when the ADCRESLT register
is read, but if there are queued conversion results in the FIFO, the Done bit will
become set again after one System Clock period.
0 – No ADC conversion has completed since the ADCRESLT register was last read.
1 – An ADC conversion has completed since the ADCRESLT register was last read.
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