CP3BT23_14 Datasheet, PDF (2/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
2 Features
CPU Features
• Fully static RISC processor core, capable of
operating from 0 to 24 MHz with zero wait/hold
states
• Minimum 41.7 ns instruction cycle time with a
24 MHz internal clock frequency, based on a 12
MHz external input
• 47 independently vectored peripheral interrupts
On-Chip Memory
• 256K bytes reprogrammable Flash program
memory
• 8K bytes Flash data memory
• 32K bytes of static RAM data memory
• Addresses up to 12M bytes of external memory
Broad Range of Hardware Communications
Peripherals
• Bluetooth Lower Link Controller (LLC)
including a shared 4.5K byte Bluetooth RAM
and 1K byte Bluetooth Sequencer RAM
• ACCESS.bus serial bus (compatible with
Philips I2C bus)
• Dual CAN interface with 15 message buffers
conforming to CAN specification 2.0B active
• 8/16-bit SPI, Microwire/Plus serial interface
• Four-channel Universal Asynchronous
Receiver/Transmitter (UART), one channel has
USART capability
• Advanced Audio Interface (AAI) to connect to
external 8/ 13-bit PCM Codecs as well as to
ISDN-Controllers through the IOM-2 interface
(slave only)
• CVSD/PCM converter supporting one
bidirectional audio connection
General-Purpose Hardware Peripherals
• 12-bit A/D Converter (ADC)
• Dual 16-bit Multi-Function Timer (MFT)
• Versatile Timer Unit with four subsystems
(VTU)
• Four-channel DMA controller
• Timing and Watchdog Unit
• Random Number Generator peripheral
Extensive Power and Clock Management
Support
• On-chip Phase Locked Loop
• Support for multiple clock options
www.ti.com
• Dual clock and reset
• Power-down modes
• Up to 56 general-purpose I/O pins (shared with
on-chip peripheral I/O)
• Programmable I/O pin characteristics: TRI-
STATE output, push-pull output, weak pull-up
input, high-impedance input
• Schmitt triggers on general-purpose inputs
• Multi-Input Wake-Up (MIWU) capability
• Flexible I/O
Power Supply
• I/O port operation at 2.5V to 3.3V
• Core logic operation at 2.5V
• On-chip power-on reset
Temperature Range
• –40°C to +85°C (Industrial)
Packages
• LQFP-128, LQFP-144
Complete Development Environment
• Pre-integrated hardware and software support
for rapid prototyping and production
• Integrated environment
• Project manager
• Multi-file C source editor
• High-level C source debugger
• Comprehensive, integrated, one-stop technical
support
Bluetooth Protocol Stack
• Applications can interface to the high-level
protocols or directly to the low-level Host
Controller Interface (HCI)
• Transport layer support allows HCI command-
based interface over UART port
• Baseband (Link Controller) hardware minimizes
the bandwidth demand on the CPU
• Link Manager (LM)
• Logical Link Control and Adaptation Protocol
(L2CAP)
• Service Discovery Protocol (SDP)
• RFCOMM Serial Port Emulation Protocol
• All packet types, piconet, and scatternet
functionality supported
2
Features
Submit Documentation Feedback
Product Folder Links: CP3BT23
Copyright © 2013–2014, Texas Instruments Incorporated