CP3BT23_14 Datasheet, PDF (183/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
19.7.3 Audio Transmit FIFO Register (ATFR)
The ATFR register shows the transmit FIFO location currently addressed by the Transmit FIFO Write
Pointer (TWP). The Audio Transmit Shift Register (ATSR) receives 8-bit or 16-bit data from the transmit
FIFO, when the ATSR is empty. In 8-bit mode, only the lower 8-bit portion of the ATSR is used, and the
upper byte is ignored (not transferred into the ATSR). In 16-bit mode, a 16-bit word is copied from the
transmit FIFO into the ATSR. The CPU bus master has write-only access to the transmit FIFO,
represented by the ATFR register. After reset, the transmit FIFO (ATFR) contains undefined data.
7
0
ATFL
15
ATFL
ATFH
8
ATFH
The Audio Transmit Low Byte field represents the lower byte of the transmit FIFO location
currently addressed by the Transmit FIFO Write Pointer (TWP).
In 16-bit mode, the Audio Transmit FIFO High Byte field represents the upper byte of the
transmit FIFO location currently addressed by the Transmit FIFO Write Pointer (TWP). In 8bit
mode, the ATFH field is not used.
19.7.4 Audio Transmit DMA Register n (ATDRn)
The ATDRn register contains the data to be transmitted in slot n, assigned for DMA support. In 8-bit
mode, only the lower 8-bit portion of the ATDRn register is used, and the upper byte is ignored (not
transferred into the ATSR). In 16bit mode, the whole 16-bit word is transferred into the ATSR. The CPU
bus master, typically a DMA controller, has writeonly access to the transmit DMA registers. After reset,
these registers are clear.
7
0
ATDL
15
ATDL
ATDH
8
ATDH
The Audio Transmit DMA Low Byte field holds the lower byte of the audio data.
In 16-bit mode, the Audio Transmit DMA High Byte field holds the upper byte of the audio
data word. In 8-bit mode, the ATDH field is ignored.
19.7.5 Audio Global Configuration Register (AGCR)
The AGCR register controls the basic operation of the interface. The CPU bus master has read/write
access to the AGCR register. After reset, this register is clear.
7
6
5
IEBC
FSS
IEFS
4
3
SCS
2
1
0
LPB
DWL
ASS
15
CLKEN
ASS
14
13
12
AAIEN
IOM2
IFS
11
10
FSL
9
8
CTF
CRF
The Asynchronous/Synchronous Mode Select bit controls whether the audio interface
operates in Asynchronous or in Synchronous mode. After reset the ASS bit is clear, so the
Synchronous mode is selected by default.
0 – Synchronous mode.
1 – Asynchronous mode.
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Advanced Audio Interface 183