CP3BT23_14 Datasheet, PDF (247/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
www.ti.com
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
Slow ClockThe Slow Clock is generated by the Triple Clock and Reset module. The clock source is either
the divided fast clock or the external 32.768 kHz crystal oscillator (if available and selected). The Slow
Clock can be used as the clock source for the two 16-bit counters. Because the Slow Clock can be
asynchronous to the System Clock, a circuit is provided to synchronize the clock signal to the high-
frequency System Clock before it is used for clocking the counters. The synchronization circuit requires
that the Slow Clock operate at no more than one-fourth the speed of the System Clock.
Limitations in Low-Power ModesThe Power Save mode uses the Slow Clock as the System Clock. In
this mode, the Slow Clock cannot be used as a clock source for the timers because that would drive both
clocks at the same frequency, and the clock ratio needed for synchronization to the System Clock would
not be maintained. However, the External Event Clock and Pulse Accumulate Mode will still work, as long
as the external event pulses are at least the size of the whole slow-clock period. Using the prescaled
System Clock will also work, but at a much slower rate than the original System Clock.
Idle and Halt modes stop the System Clock (the high-frequency and/or low-frequency clock) completely. If
the System Clock is stopped, the timer stops counting until the System Clock resumes operation.
In the Idle or Halt mode, the System Clock stops completely, which stops the operation of the timers. In
that case, the timers stop counting until the System Clock resumes operation.
25.2 TIMER OPERATING MODES
Each timer/counter unit can be configured to operate in any of the following modes:
• Processor-Independent Pulse Width Modulation (PWM) mode
• Dual-Input Capture mode
• Dual Independent Timer mode
• Single-Input Capture and Single Timer mode
At reset, the timers are disabled. To configure and start the timers, software must write a set of values to
the registers that control the timers. The registers are described in Section 25.5.
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