CP3BT23_14 Datasheet, PDF (64/324 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

CP3BT23
SNOSCX3A – JULY 2013 – REVISED JANUARY 2014
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IRQ Number
IRQ3
IRQ2
IRQ1
IRQ0
Table 10-2. Maskable Interrupts Assignment (continued)
Random Number Generator (RNG)
Reserved
Flash Program/Data Memory
Reserved
Description
All reserved interrupt vectors should point to default or error interrupt handlers.
10.5 NESTED INTERRUPTS
Nested NMI interrupts are always enabled. Nested maskable interrupts are disabled by default, however
an interrupt handler can allow nested maskable interrupts by setting the I bit in the PSR. The LPR
instruction is used to set the I bit.
Nesting of specific maskable interrupts can be allowed by disabling interrupts from sources for which
nesting is not allowed, before setting the I bit. Individual maskable interrupt sources can be disabled using
the IENAM0 and IENAM1 registers.
Any number of levels of nested interrupts are allowed, limited only by the available memory for the
interrupt stack.
64
Interrupts
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